Searched refs:read_aux_reg (Results 1 – 12 of 12) sorted by relevance
95 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_read_counter()97 result = (uint64_t) (read_aux_reg(ARC_REG_PCT_SNAPH)) << 32; in arc_pmu_read_counter()98 result |= read_aux_reg(ARC_REG_PCT_SNAPL); in arc_pmu_read_counter()202 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_enable()210 tmp = read_aux_reg(ARC_REG_PCT_CONTROL); in arc_pmu_disable()278 read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx)); in arc_pmu_start()298 read_aux_reg(ARC_REG_PCT_INT_CTRL) & ~(1 << idx)); in arc_pmu_stop()383 active_ints = read_aux_reg(ARC_REG_PCT_INT_ACT); in arc_pmu_intr()403 read_aux_reg(ARC_REG_PCT_INT_CTRL) | (1 << idx)); in arc_pmu_intr()489 cc_name.indiv.word0 = read_aux_reg(ARC_REG_CC_NAME0); in arc_pmu_device_probe()[all …]
57 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); in read_arc_build_cfg_regs()63 perip_space = read_aux_reg(AUX_NON_VOL) & 0xF0000000; in read_arc_build_cfg_regs()69 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ in read_arc_build_cfg_regs()70 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ in read_arc_build_cfg_regs()71 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */ in read_arc_build_cfg_regs()72 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; in read_arc_build_cfg_regs()73 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ in read_arc_build_cfg_regs()85 bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR); in read_arc_build_cfg_regs()92 bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR); in read_arc_build_cfg_regs()
87 stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK); in arc_counter_read()90 stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK); in arc_counter_read()170 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); in arc_counter_read()
59 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_mask()68 ienb = read_aux_reg(AUX_IENABLE); in arc_irq_unmask()
50 tmp = read_aux_reg(0xa); in arc_init_IRQ()68 tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF; in arc_init_IRQ()
55 ipi_was_pending = read_aux_reg(ARC_REG_MCIP_READBACK); in mcip_ipi_send()86 copy = cpu = read_aux_reg(ARC_REG_MCIP_READBACK); /* 1,2,4,8... */ in mcip_ipi_clear()
403 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); in __before_dc_op()414 while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) in __after_dc_op()480 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ in __ic_entire_inv()555 ctrl = read_aux_reg(ARC_REG_SLC_CTRL); in slc_op()578 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); in slc_op()966 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM); in arc_cache_init()971 while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY); in arc_cache_init()973 read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE); in arc_cache_init()
129 idx = read_aux_reg(ARC_REG_TLBINDEX); in tlb_entry_lkup()177 idx = read_aux_reg(ARC_REG_TLBINDEX); in utlb_invalidate()561 asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff; in create_tlb()758 tmp = read_aux_reg(ARC_REG_MMU_BCR); in read_decode_mmu_bcr()889 write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID)); in do_tlb_overlap_fault()901 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()964 mmu_asid = read_aux_reg(ARC_REG_PID) & 0xff; in tlb_paranoid_check()
119 #define read_aux_reg(reg) __builtin_arc_lr(reg) macro127 #define read_aux_reg(reg) \ macro175 tmp = read_aux_reg(reg); \
71 unsigned int irqact = read_aux_reg(AUX_IRQ_ACT); in arch_local_irq_enable()
356 pgd_t *pgd_base = (pgd_t *) read_aux_reg(ARC_REG_SCRATCH_DATA0); \
402 unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; in axs103_early_init()