Searched refs:ramfc (Results 1 - 19 of 19) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Ddmag84.c66 nvkm_kmap(chan->ramfc); g84_fifo_dma_new()
67 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); g84_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); g84_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); g84_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); g84_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); g84_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); g84_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); g84_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); g84_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); g84_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); g84_fifo_dma_new()
77 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); g84_fifo_dma_new()
78 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | g84_fifo_dma_new()
81 nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); g84_fifo_dma_new()
82 nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); g84_fifo_dma_new()
83 nvkm_done(chan->ramfc); g84_fifo_dma_new()
H A Ddmanv50.c66 nvkm_kmap(chan->ramfc); nv50_fifo_dma_new()
67 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); nv50_fifo_dma_new()
68 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); nv50_fifo_dma_new()
69 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); nv50_fifo_dma_new()
70 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); nv50_fifo_dma_new()
71 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); nv50_fifo_dma_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); nv50_fifo_dma_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); nv50_fifo_dma_new()
74 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); nv50_fifo_dma_new()
75 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); nv50_fifo_dma_new()
76 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); nv50_fifo_dma_new()
77 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); nv50_fifo_dma_new()
78 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | nv50_fifo_dma_new()
81 nvkm_done(chan->ramfc); nv50_fifo_dma_new()
H A Dgpfifog84.c70 nvkm_kmap(chan->ramfc); g84_fifo_gpfifo_new()
71 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); g84_fifo_gpfifo_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); g84_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); g84_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); g84_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); g84_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); g84_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); g84_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); g84_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | g84_fifo_gpfifo_new()
82 nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); g84_fifo_gpfifo_new()
83 nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); g84_fifo_gpfifo_new()
84 nvkm_done(chan->ramfc); g84_fifo_gpfifo_new()
H A Ddmanv10.c73 chan->ramfc = chan->base.chid * 32; nv10_fifo_dma_new()
75 nvkm_kmap(imem->ramfc); nv10_fifo_dma_new()
76 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nv10_fifo_dma_new()
77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); nv10_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nv10_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, nv10_fifo_dma_new()
86 nvkm_done(imem->ramfc); nv10_fifo_dma_new()
H A Ddmanv17.c74 chan->ramfc = chan->base.chid * 64; nv17_fifo_dma_new()
76 nvkm_kmap(imem->ramfc); nv17_fifo_dma_new()
77 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nv17_fifo_dma_new()
78 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); nv17_fifo_dma_new()
79 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nv17_fifo_dma_new()
80 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, nv17_fifo_dma_new()
87 nvkm_done(imem->ramfc); nv17_fifo_dma_new()
H A Dgpfifonv50.c70 nvkm_kmap(chan->ramfc); nv50_fifo_gpfifo_new()
71 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); nv50_fifo_gpfifo_new()
72 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); nv50_fifo_gpfifo_new()
73 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); nv50_fifo_gpfifo_new()
74 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); nv50_fifo_gpfifo_new()
75 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); nv50_fifo_gpfifo_new()
76 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); nv50_fifo_gpfifo_new()
77 nvkm_wo32(chan->ramfc, 0x78, 0x00000000); nv50_fifo_gpfifo_new()
78 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); nv50_fifo_gpfifo_new()
79 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | nv50_fifo_gpfifo_new()
82 nvkm_done(chan->ramfc); nv50_fifo_gpfifo_new()
H A Ddmanv40.c76 nvkm_kmap(imem->ramfc); nv40_fifo_dma_engine_fini()
77 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); nv40_fifo_dma_engine_fini()
78 nvkm_done(imem->ramfc); nv40_fifo_dma_engine_fini()
107 nvkm_kmap(imem->ramfc); nv40_fifo_dma_engine_init()
108 nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); nv40_fifo_dma_engine_init()
109 nvkm_done(imem->ramfc); nv40_fifo_dma_engine_init()
219 chan->ramfc = chan->base.chid * 128; nv40_fifo_dma_new()
221 nvkm_kmap(imem->ramfc); nv40_fifo_dma_new()
222 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nv40_fifo_dma_new()
223 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); nv40_fifo_dma_new()
224 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nv40_fifo_dma_new()
225 nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | nv40_fifo_dma_new()
232 nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); nv40_fifo_dma_new()
233 nvkm_done(imem->ramfc); nv40_fifo_dma_new()
H A Ddmanv04.c75 struct nvkm_memory *fctx = device->imem->ramfc; nv04_fifo_dma_fini()
79 u32 data = chan->ramfc; nv04_fifo_dma_fini()
93 c = fifo->ramfc; nv04_fifo_dma_fini()
102 c = fifo->ramfc; nv04_fifo_dma_fini()
139 const struct nv04_fifo_ramfc *c = fifo->ramfc; nv04_fifo_dma_dtor()
141 nvkm_kmap(imem->ramfc); nv04_fifo_dma_dtor()
143 nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); nv04_fifo_dma_dtor()
145 nvkm_done(imem->ramfc); nv04_fifo_dma_dtor()
197 chan->ramfc = chan->base.chid * 32; nv04_fifo_dma_new()
199 nvkm_kmap(imem->ramfc); nv04_fifo_dma_new()
200 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nv04_fifo_dma_new()
201 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); nv04_fifo_dma_new()
202 nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); nv04_fifo_dma_new()
203 nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, nv04_fifo_dma_new()
210 nvkm_done(imem->ramfc); nv04_fifo_dma_new()
H A Dnv04.h16 const struct nv04_fifo_ramfc *ramfc; member in struct:nv04_fifo
H A Dchannv04.h10 u32 ramfc; member in struct:nv04_fifo_chan
H A Dchannv50.h11 struct nvkm_gpuobj *ramfc; member in struct:nv50_fifo_chan
H A Dnv17.c58 struct nvkm_memory *ramfc = imem->ramfc; nv17_fifo_init() local
67 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | nv17_fifo_init()
H A Dnv40.c68 struct nvkm_memory *ramfc = imem->ramfc; nv40_fifo_init() local
95 nvkm_memory_addr(ramfc)) >> 16) | nv40_fifo_init()
H A Dnv04.c304 struct nvkm_memory *ramfc = imem->ramfc; nv04_fifo_init() local
313 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); nv04_fifo_init()
327 int index, int nr, const struct nv04_fifo_ramfc *ramfc, nv04_fifo_new_()
335 fifo->ramfc = ramfc; nv04_fifo_new_()
326 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, int index, int nr, const struct nv04_fifo_ramfc *ramfc, struct nvkm_fifo **pfifo) nv04_fifo_new_() argument
H A Dchannv50.c198 u64 addr = chan->ramfc->addr >> 12; nv50_fifo_chan_init()
214 nvkm_gpuobj_del(&chan->ramfc); nv50_fifo_chan_dtor()
251 &chan->ramfc); nv50_fifo_chan_ctor()
H A Dchang84.c210 u64 addr = chan->ramfc->addr >> 8; g84_fifo_chan_init()
276 &chan->ramfc); g84_fifo_chan_ctor()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dinstmem.h17 struct nvkm_memory *ramfc; member in struct:nvkm_instmem
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv04.c180 &imem->base.ramfc); nv04_instmem_oneinit()
197 nvkm_memory_del(&imem->base.ramfc); nv04_instmem_dtor()
H A Dnv40.c201 &imem->base.ramfc); nv40_instmem_oneinit()
212 nvkm_memory_del(&imem->base.ramfc); nv40_instmem_dtor()

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