Searched refs:pll_info (Results 1 – 4 of 4) sorted by relevance
83 const struct ingenic_cgu_pll_info *pll_info; in ingenic_pll_recalc_rate() local91 pll_info = &clk_info->pll; in ingenic_pll_recalc_rate()94 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()97 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()98 m += pll_info->m_offset; in ingenic_pll_recalc_rate()99 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()100 n += pll_info->n_offset; in ingenic_pll_recalc_rate()101 od_enc = ctl >> pll_info->od_shift; in ingenic_pll_recalc_rate()102 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()103 bypass = !!(ctl & BIT(pll_info->bypass_bit)); in ingenic_pll_recalc_rate()[all …]
733 uint16_t pll_info; in radeon_combios_get_clock_info() local741 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); in radeon_combios_get_clock_info()742 if (pll_info) { in radeon_combios_get_clock_info()743 rev = RBIOS8(pll_info); in radeon_combios_get_clock_info()746 p1pll->reference_freq = RBIOS16(pll_info + 0xe); in radeon_combios_get_clock_info()747 p1pll->reference_div = RBIOS16(pll_info + 0x10); in radeon_combios_get_clock_info()748 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); in radeon_combios_get_clock_info()749 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); in radeon_combios_get_clock_info()754 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); in radeon_combios_get_clock_info()755 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); in radeon_combios_get_clock_info()[all …]
46 struct pll_info { struct137 struct pll_info pll_limits;
137 struct pll_info { struct341 struct pll_info pll;