Searched refs:outpw (Results 1 - 7 of 7) sorted by relevance

/linux-4.4.14/drivers/net/fddi/skfp/
H A Dfplustm.c160 outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
198 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */ set_recvptr()
199 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */ set_recvptr()
200 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */ set_recvptr()
201 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */ set_recvptr()
207 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ; set_recvptr()
208 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ; set_recvptr()
209 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ; set_recvptr()
210 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ; set_recvptr()
213 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ; set_recvptr()
214 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rbc_ram_end-1) ; set_recvptr()
215 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rbc_ram_end-1) ; set_recvptr()
216 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ; set_recvptr()
225 outpw(FM_A(FM_CMDREG2),FM_IRSTQ) ; /* reset transmit queues */ set_txptr()
230 outpw(FM_A(FM_RPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* RPXA0 */ set_txptr()
231 outpw(FM_A(FM_SWPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* SWPXA0 */ set_txptr()
232 outpw(FM_A(FM_WPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* WPXA0 */ set_txptr()
233 outpw(FM_A(FM_EAA0),smc->hw.fp.fifo.rx2_fifo_start-1) ; /* EAA0 */ set_txptr()
239 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_s_start) ; set_txptr()
240 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_s_start) ; set_txptr()
241 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_s_start) ; set_txptr()
242 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ; set_txptr()
245 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_a0_start-1) ; set_txptr()
246 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_a0_start-1) ; set_txptr()
247 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_a0_start-1) ; set_txptr()
248 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ; set_txptr()
264 outpw(FM_A(FM_RPXA1),rbc_ram_addr) ; /* a1-send pointer */ init_rbc()
265 outpw(FM_A(FM_WPXA1),rbc_ram_addr) ; init_rbc()
266 outpw(FM_A(FM_SWPXA1),rbc_ram_addr) ; init_rbc()
267 outpw(FM_A(FM_EAA1),rbc_ram_addr) ; init_rbc()
300 outpw(FM_A(FM_TSYNC),(unsigned int) (((-sync_bw) >> 5) & 0xffff) ) ; set_formac_tsync()
340 outpw(FM_A(FM_FCNTR),0) ; mac_counter_init()
341 outpw(FM_A(FM_LCNTR),0) ; mac_counter_init()
342 outpw(FM_A(FM_ECNTR),0) ; mac_counter_init()
359 outpw(FM_A(FM_SAID),my_said) ; /* set short address */ set_formac_addr()
360 outpw(FM_A(FM_LAIL),(unsigned short)((smc->hw.fddi_home_addr.a[4]<<8) + set_formac_addr()
362 outpw(FM_A(FM_LAIC),(unsigned short)((smc->hw.fddi_home_addr.a[2]<<8) + set_formac_addr()
364 outpw(FM_A(FM_LAIM),(unsigned short)((smc->hw.fddi_home_addr.a[0]<<8) + set_formac_addr()
367 outpw(FM_A(FM_SAGP),my_sagp) ; /* set short group address */ set_formac_addr()
369 outpw(FM_A(FM_LAGL),(unsigned short)((smc->hw.fp.group_addr.a[4]<<8) + set_formac_addr()
371 outpw(FM_A(FM_LAGC),(unsigned short)((smc->hw.fp.group_addr.a[2]<<8) + set_formac_addr()
373 outpw(FM_A(FM_LAGM),(unsigned short)((smc->hw.fp.group_addr.a[0]<<8) + set_formac_addr()
377 outpw(FM_A(FM_TREQ1),(unsigned short)(t_requ>>16)) ; set_formac_addr()
378 outpw(FM_A(FM_TREQ0),(unsigned short)t_requ) ; set_formac_addr()
414 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; copy_tx_mac()
420 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */ copy_tx_mac()
463 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */ directed_beacon()
466 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF) ; directed_beacon()
496 outpw(FM_A(FM_SACL),smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF) ; build_claim_beacon()
511 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF) ; build_claim_beacon()
530 outpw(FM_A(FM_EACB),smc->hw.fp.fifo.rx1_fifo_start-1) ; build_claim_beacon()
532 outpw(FM_A(FM_WPXSF),0) ; build_claim_beacon()
533 outpw(FM_A(FM_RPXSF),0) ; build_claim_beacon()
541 outpw(FM_A(FM_CMDREG1),FM_ICLLR) ; /* clear receive lock */ formac_rcv_restart()
546 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */ formac_tx_restart()
547 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */ formac_tx_restart()
553 outpw(FM_A(FM_IMSK1U),(unsigned short)~mac_imsk1u); enable_formac()
554 outpw(FM_A(FM_IMSK1L),(unsigned short)~mac_imsk1l); enable_formac()
555 outpw(FM_A(FM_IMSK2U),(unsigned short)~mac_imsk2u); enable_formac()
556 outpw(FM_A(FM_IMSK2L),(unsigned short)~mac_imsk2l); enable_formac()
557 outpw(FM_A(FM_IMSK3U),(unsigned short)~mac_imsk3u); enable_formac()
558 outpw(FM_A(FM_IMSK3L),(unsigned short)~mac_imsk3l); enable_formac()
598 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMS)) ;
601 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMA0)) ;
633 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMS)) ;
636 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMA0)) ;
644 outpw(FM_A(FM_IMSK1U),MW) ; disable_formac()
645 outpw(FM_A(FM_IMSK1L),MW) ; disable_formac()
646 outpw(FM_A(FM_IMSK2U),MW) ; disable_formac()
647 outpw(FM_A(FM_IMSK2L),MW) ; disable_formac()
648 outpw(FM_A(FM_IMSK3U),MW) ; disable_formac()
649 outpw(FM_A(FM_IMSK3L),MW) ; disable_formac()
665 outpw(FM_A(FM_CMDREG2),FM_IACTR) ; mac_ring_up()
800 outpw(FM_A(FM_IMSK2U),~mac_imsk2u) ; mac2_irq()
831 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;/* abort current transmit activity */ formac_offline()
903 outpw(FM_A(FM_MDREG1),FM_MINIT) ; /* FORMAC+ init mode */ init_mac()
905 outpw(FM_A(FM_MDREG1),FM_MMEMACT) ; /* FORMAC+ memory activ mode */ init_mac()
907 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ; init_mac()
933 outpw(FM_A(FM_FRMTHR),14<<12) ; /* switch on */ init_mac()
936 outpw(FM_A(FM_MDREG1),MDR1INIT | FM_SELRA | smc->hw.fp.rx_mode) ; init_mac()
937 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ; init_mac()
938 outpw(FM_A(FM_MDREG3),smc->hw.fp.mdr3init) ; init_mac()
939 outpw(FM_A(FM_FRSELREG),smc->hw.fp.frselreg_init) ; init_mac()
952 outpw(FM_A(FM_TMAX),(u_short)t_max) ; init_mac()
956 outpw(FM_A(FM_TVX), (u_short) (- US2BCLK(52))/255 & MB) ; init_mac()
958 outpw(FM_A(FM_TVX), init_mac()
962 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */ init_mac()
963 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */ init_mac()
964 outpw(FM_A(FM_CMDREG1),FM_ICLLR); /* clear receive lock */ init_mac()
967 outpw(FM_A(FM_UNLCKDLY),(0xff|(0xff<<8))) ; init_mac()
1017 outpw(FM_A(FM_IMSK2U),~(mac_imsk2u | mac_beacon_imsk2u)) ; sm_mac_check_beacon_claim()
1209 outpw(FM_A(FM_AFCMD),FM_IINV_CAM) ; mac_update_multicast()
1216 outpw(FM_A(FM_AFMASK2),0xffff) ; mac_update_multicast()
1217 outpw(FM_A(FM_AFMASK1),(u_short) ~((fu[0] << 8) + fu[1])) ; mac_update_multicast()
1218 outpw(FM_A(FM_AFMASK0),(u_short) ~((fu[2] << 8) + fu[3])) ; mac_update_multicast()
1219 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ; mac_update_multicast()
1220 outpw(FM_A(FM_AFCOMP2), 0xc000) ; mac_update_multicast()
1221 outpw(FM_A(FM_AFCOMP1), 0x0000) ; mac_update_multicast()
1222 outpw(FM_A(FM_AFCOMP0), 0x0000) ; mac_update_multicast()
1223 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ; mac_update_multicast()
1229 outpw(FM_A(FM_AFMASK0),0xffff) ; mac_update_multicast()
1230 outpw(FM_A(FM_AFMASK1),0xffff) ; mac_update_multicast()
1231 outpw(FM_A(FM_AFMASK2),0xffff) ; mac_update_multicast()
1232 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ; mac_update_multicast()
1241 outpw(FM_A(FM_AFCOMP2), mac_update_multicast()
1243 outpw(FM_A(FM_AFCOMP1), mac_update_multicast()
1245 outpw(FM_A(FM_AFCOMP0), mac_update_multicast()
1247 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ; mac_update_multicast()
1334 outpw(ADDR(B2_RTM_CRTL),TIM_CL_IRQ) ; /* clear IRQ */ rtm_irq()
1336 outpw(FM_A(FM_CMDREG1),FM_ICL) ; /* force claim */ rtm_irq()
1342 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable RTM monitoring */ rtm_irq()
1348 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable IRQ */ rtm_init()
H A Dhwt.c82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */ hwt_start()
103 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ; hwt_stop()
104 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ; hwt_stop()
205 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ; hwt_quick_read()
208 outpw(ADDR(B2_TI_CRTL), TIM_START) ; hwt_quick_read()
H A Dpcmplc.c430 outpw(PLC(p,PL_CNTRL_B),0) ; plc_init()
431 outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ; plc_init()
432 outpw(PLC(p,PL_CNTRL_A),0) ; plc_init()
443 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_S) ; plc_init()
445 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_S) ; plc_init()
446 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_S) ; plc_init()
450 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_U) ; plc_init()
452 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_U) ; plc_init()
453 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_U) ; plc_init()
462 outpw(PLC(p,pltm[i].timer),pltm[i].para) ; plc_init()
466 outpw(PLC(p,PL_INTR_MASK),plc_imsk_na); /* enable non active irq's */ plc_init()
477 outpw(PLC(p,PL_CNTRL_B),PL_CLASS_S) ; plc_init()
494 outpw(port,val) ; plc_go_state()
495 outpw(port,val | state) ; plc_go_state()
553 outpw(PLC(np,PL_VECTOR_LEN),len-1) ; /* len=nr-1 */ plc_send_bits()
554 outpw(PLC(np,PL_XMIT_VECTOR),n) ; plc_send_bits()
723 outpw(PLC(np,PL_CNTRL_A),0) ; pcm_fsm()
775 outpw(PLC(np,PL_INTR_MASK),plc_imsk_na) ; pcm_fsm()
896 outpw(PLC(np,PL_CNTRL_B),i) ; /* must be cleared */ pcm_fsm()
897 outpw(PLC(np,PL_CNTRL_B),i | PL_RLBP) ; pcm_fsm()
989 outpw(PLC(np,PL_INTR_MASK),plc_imsk_act) ;
1016 outpw(PLC(np,PL_CNTRL_A),PL_SC_BYPASS) ;
1063 outpw(PLC(phy,PL_CNTRL_B),cntrl) ; sm_ph_linestate()
1240 outpw(PLC(np,PL_LE_THRESHOLD),threshold) ; sm_ph_lem_start()
1352 outpw(PLC((int)phy->np,PL_LC_LENGTH), TP_LC_LENGTH ) ; pc_rcode_actions()
1356 outpw(PLC((int)phy->np,PL_LC_LENGTH), TP_LC_LONGLN ) ; pc_rcode_actions()
1700 outpw(PLC(np,PL_INTR_MASK),corr_mask); plc_irq()
H A Ddrvfbi.c102 outpw(FM_A(FM_MDREG1),FM_MINIT) ; card_start()
118 outpw(PCI_C(PCI_STATUS), word | PCI_ERRBITS) ; card_start()
172 outpw(FM_A(FM_MDREG1),FM_MINIT) ; card_stop()
556 outpw(ADDR(B2_WDOG_CRTL),TIM_START) ; /* Start timer. */ smt_start_watchdog()
570 outpw(ADDR(B2_WDOG_CRTL),TIM_STOP) ; /* Stop timer. */ smt_stop_watchdog()
/linux-4.4.14/drivers/net/fddi/skfp/h/
H A Dtypes.h36 #define outpw(p,s) iowrite16(s,p) macro
H A Dskfbi.h1036 #define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask)))
1037 #define SET(io,mask) outpw((io),inpw(io)|(mask))
1039 #define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val))
1050 #define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma))
1051 #define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma))
1057 #define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
1058 outpw(FM_A(FM_MDRL),(unsigned int)(dd))
1084 #define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
/linux-4.4.14/drivers/scsi/
H A Dadvansys.c84 #define outpw(port, word) outw((word), (port)) macro
826 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
827 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
831 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
833 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
835 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
839 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
844 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
851 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
855 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
859 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
861 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
865 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
867 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
869 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
871 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
3856 * is "transparently" byte-swapped by outpw() and written AscMemWordCopyPtrToLram()
3859 outpw(iop_base + IOP_RAM_DATA, AscMemWordCopyPtrToLram()
3878 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ AscMemDWordCopyPtrToLram()
3879 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ AscMemDWordCopyPtrToLram()
7959 outpw(iop_base + IOP_RAM_DATA, DvcPutScsiQ()

Completed in 253 milliseconds