| /linux-4.4.14/drivers/video/fbdev/ |
| H A D | da8xx-fb.c | 148 static void lcdc_write(unsigned int val, unsigned int addr) lcdc_write() function
273 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); lcd_enable_raster()
278 lcdc_write(0, LCD_CLK_RESET_REG); lcd_enable_raster()
284 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); lcd_enable_raster()
295 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); lcd_disable_raster()
337 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); lcd_blit()
341 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); lcd_blit()
342 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); lcd_blit()
343 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); lcd_blit()
344 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); lcd_blit()
356 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); lcd_blit()
359 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); lcd_blit()
360 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); lcd_blit()
363 lcdc_write(reg_dma, LCD_DMA_CTRL_REG); lcd_blit()
364 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); lcd_blit()
400 lcdc_write(reg, LCD_DMA_CTRL_REG); lcd_cfg_dma()
413 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); lcd_cfg_ac_bias()
425 lcdc_write(reg, LCD_RASTER_TIMING_0_REG); lcd_cfg_horizontal_sync()
439 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); lcd_cfg_horizontal_sync()
452 lcdc_write(reg, LCD_RASTER_TIMING_1_REG); lcd_cfg_vertical_sync()
494 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); lcd_cfg_display()
497 lcdc_write(reg, LCD_RASTER_CTRL_REG); lcd_cfg_display()
518 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); lcd_cfg_display()
555 lcdc_write(reg, LCD_RASTER_TIMING_0_REG); lcd_cfg_frame_buffer()
561 lcdc_write(reg, LCD_RASTER_TIMING_1_REG); lcd_cfg_frame_buffer()
567 lcdc_write(reg, LCD_RASTER_TIMING_2_REG); lcd_cfg_frame_buffer()
598 lcdc_write(reg, LCD_RASTER_CTRL_REG); lcd_cfg_frame_buffer()
697 lcdc_write(0, LCD_DMA_CTRL_REG); da8xx_fb_lcd_reset()
698 lcdc_write(0, LCD_RASTER_CTRL_REG); da8xx_fb_lcd_reset()
701 lcdc_write(0, LCD_INT_ENABLE_SET_REG); da8xx_fb_lcd_reset()
703 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); da8xx_fb_lcd_reset()
704 lcdc_write(0, LCD_CLK_RESET_REG); da8xx_fb_lcd_reset()
726 lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) | da8xx_fb_config_clk_divider()
730 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | da8xx_fb_config_clk_divider()
793 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | lcd_init()
796 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & lcd_init()
826 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | lcd_init()
840 lcdc_write(stat, LCD_MASKED_STAT_REG); lcdc_irq_handler_rev02()
851 lcdc_write(stat, LCD_MASKED_STAT_REG); lcdc_irq_handler_rev02()
854 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); lcdc_irq_handler_rev02()
859 lcdc_write(stat, LCD_MASKED_STAT_REG); lcdc_irq_handler_rev02()
863 lcdc_write(par->dma_start, lcdc_irq_handler_rev02()
865 lcdc_write(par->dma_end, lcdc_irq_handler_rev02()
873 lcdc_write(par->dma_start, lcdc_irq_handler_rev02()
875 lcdc_write(par->dma_end, lcdc_irq_handler_rev02()
890 lcdc_write(0, LCD_END_OF_INT_IND_REG); lcdc_irq_handler_rev02()
903 lcdc_write(stat, LCD_STAT_REG); lcdc_irq_handler_rev01()
914 lcdc_write(stat, LCD_STAT_REG); lcdc_irq_handler_rev01()
919 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); lcdc_irq_handler_rev01()
924 lcdc_write(stat, LCD_STAT_REG); lcdc_irq_handler_rev01()
928 lcdc_write(par->dma_start, lcdc_irq_handler_rev01()
930 lcdc_write(par->dma_end, lcdc_irq_handler_rev01()
938 lcdc_write(par->dma_start, lcdc_irq_handler_rev01()
940 lcdc_write(par->dma_end, lcdc_irq_handler_rev01()
1093 lcdc_write(0, LCD_RASTER_CTRL_REG); fb_remove()
1096 lcdc_write(0, LCD_DMA_CTRL_REG); fb_remove()
1248 lcdc_write(par->dma_start, da8xx_pan_display()
1250 lcdc_write(par->dma_end, da8xx_pan_display()
1253 lcdc_write(par->dma_start, da8xx_pan_display()
1255 lcdc_write(par->dma_end, da8xx_pan_display()
1295 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); da8xxfb_set_par()
1296 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); da8xxfb_set_par()
1297 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); da8xxfb_set_par()
1298 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); da8xxfb_set_par()
1594 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG); lcd_context_restore()
1595 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG); lcd_context_restore()
1598 lcdc_write(reg_context.ctrl, LCD_CTRL_REG); lcd_context_restore()
1599 lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG); lcd_context_restore()
1600 lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG); lcd_context_restore()
1601 lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG); lcd_context_restore()
1602 lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG); lcd_context_restore()
1603 lcdc_write(reg_context.dma_frm_buf_base_addr_0, lcd_context_restore()
1605 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0, lcd_context_restore()
1607 lcdc_write(reg_context.dma_frm_buf_base_addr_1, lcd_context_restore()
1609 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1, lcd_context_restore()
1611 lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG); lcd_context_restore()
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| H A D | sh_mobile_lcdcfb.c | 319 static void lcdc_write(struct sh_mobile_lcdc_priv *priv, lcdc_write() function
409 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); lcdc_sys_write_index()
411 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | lcdc_sys_write_index()
420 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW); lcdc_sys_write_data()
422 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | lcdc_sys_write_data()
431 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR); lcdc_sys_read_data()
433 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA | lcdc_sys_read_data()
735 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE); sh_mobile_lcdc_irq()
775 lcdc_write(ch->lcdc, _LDINTR, ldintr); sh_mobile_lcdc_wait_for_vsync()
793 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO); sh_mobile_lcdc_start_stop()
795 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO); sh_mobile_lcdc_start_stop()
811 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */ sh_mobile_lcdc_start_stop()
871 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index)); sh_mobile_lcdc_overlay_setup()
873 lcdc_write(ovl->channel->lcdc, LDBCR, sh_mobile_lcdc_overlay_setup()
936 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index)); sh_mobile_lcdc_overlay_setup()
952 lcdc_write(ovl->channel->lcdc, LDBCR, sh_mobile_lcdc_overlay_setup()
972 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled); __sh_mobile_lcdc_start()
976 lcdc_write(priv, _LDINTR, 0); __sh_mobile_lcdc_start()
1003 lcdc_write(priv, _LDDCKR, tmp); __sh_mobile_lcdc_start()
1004 lcdc_write(priv, _LDDCKSTPR, 0); __sh_mobile_lcdc_start()
1041 lcdc_write(priv, _LDINTR, LDINTR_FE); __sh_mobile_lcdc_start()
1066 lcdc_write(priv, _LDDDSR, tmp); __sh_mobile_lcdc_start()
1069 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE); __sh_mobile_lcdc_start()
1089 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR); sh_mobile_lcdc_start()
1543 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index)); sh_mobile_lcdc_overlay_pan()
1548 lcdc_write(ovl->channel->lcdc, LDBCR, sh_mobile_lcdc_overlay_pan()
1869 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS); sh_mobile_lcdc_pan()
1871 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS); sh_mobile_lcdc_pan()
2361 lcdc_write(priv, _LDCNT1R, 0); sh_mobile_lcdc_runtime_suspend()
|
| /linux-4.4.14/drivers/gpu/drm/shmobile/ |
| H A D | shmob_drm_crtc.c | 88 lcdc_write(sdev, LDMT1R, value); shmob_drm_crtc_setup_geometry()
99 lcdc_write(sdev, LDMT2R, value); shmob_drm_crtc_setup_geometry()
105 lcdc_write(sdev, LDMT3R, value); shmob_drm_crtc_setup_geometry()
110 lcdc_write(sdev, LDHCNR, value); shmob_drm_crtc_setup_geometry()
114 lcdc_write(sdev, LDHSYNR, value); shmob_drm_crtc_setup_geometry()
119 lcdc_write(sdev, LDHAJR, value); shmob_drm_crtc_setup_geometry()
123 lcdc_write(sdev, LDVLNR, value); shmob_drm_crtc_setup_geometry()
127 lcdc_write(sdev, LDVSYNR, value); shmob_drm_crtc_setup_geometry()
137 lcdc_write(sdev, LDCNT2R, value | LDCNT2R_DO); shmob_drm_crtc_start_stop()
139 lcdc_write(sdev, LDCNT2R, value & ~LDCNT2R_DO); shmob_drm_crtc_start_stop()
152 lcdc_write(sdev, LDDCKSTPR, LDDCKSTPR_DCKSTP); shmob_drm_crtc_start_stop()
187 lcdc_write(sdev, LDCNT2R, lcdc_read(sdev, LDCNT2R) | LDCNT2R_BR); shmob_drm_crtc_start()
189 lcdc_write(sdev, LDCNT2R, LDCNT2R_ME); shmob_drm_crtc_start()
193 lcdc_write(sdev, LDINTR, 0); shmob_drm_crtc_start()
196 lcdc_write(sdev, LDPMR, 0); shmob_drm_crtc_start()
203 lcdc_write(sdev, LDDCKPAT1R, 0); shmob_drm_crtc_start()
204 lcdc_write(sdev, LDDCKPAT2R, (1 << (idata->clk_div / 2)) - 1); shmob_drm_crtc_start()
212 lcdc_write(sdev, LDDCKR, value); shmob_drm_crtc_start()
213 lcdc_write(sdev, LDDCKSTPR, 0); shmob_drm_crtc_start()
222 lcdc_write(sdev, LDDFR, format->lddfr | LDDFR_CF1); shmob_drm_crtc_start()
223 lcdc_write(sdev, LDMLSR, scrtc->line_size); shmob_drm_crtc_start()
224 lcdc_write(sdev, LDSA1R, scrtc->dma[0]); shmob_drm_crtc_start()
226 lcdc_write(sdev, LDSA2R, scrtc->dma[1]); shmob_drm_crtc_start()
227 lcdc_write(sdev, LDSM1R, 0); shmob_drm_crtc_start()
248 lcdc_write(sdev, LDDDSR, value); shmob_drm_crtc_start()
257 lcdc_write(sdev, LDCNT1R, LDCNT1R_DE);
282 lcdc_write(sdev, LDCNT1R, 0); shmob_drm_crtc_stop()
342 lcdc_write(sdev, LDRCNTR, lcdc_read(sdev, LDRCNTR) ^ LDRCNTR_MRS); shmob_drm_crtc_update_base()
637 lcdc_write(sdev, LDINTR, ldintr); shmob_drm_crtc_enable_vblank()
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| H A D | shmob_drm_plane.c | 131 lcdc_write(sdev, LDBCR, LDBCR_UPC(splane->index)); __shmob_drm_plane_setup()
135 lcdc_write(sdev, LDBnBSIFR(splane->index), format); __shmob_drm_plane_setup()
137 lcdc_write(sdev, LDBnBSSZR(splane->index), __shmob_drm_plane_setup()
140 lcdc_write(sdev, LDBnBLOCR(splane->index), __shmob_drm_plane_setup()
143 lcdc_write(sdev, LDBnBSMWR(splane->index), __shmob_drm_plane_setup()
148 lcdc_write(sdev, LDBnBSAYR(splane->index), splane->dma[0]); __shmob_drm_plane_setup()
150 lcdc_write(sdev, LDBnBSACR(splane->index), splane->dma[1]); __shmob_drm_plane_setup()
152 lcdc_write(sdev, LDBCR, __shmob_drm_plane_setup()
218 lcdc_write(sdev, LDBnBSIFR(splane->index), 0); shmob_drm_plane_disable()
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| H A D | shmob_drm_drv.c | 223 lcdc_write(sdev, LDINTR, status ^ LDINTR_STATUS_MASK); shmob_drm_irq()
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| H A D | shmob_drm_regs.h | 285 static inline void lcdc_write(struct shmob_drm_device *sdev, u32 reg, u32 data) lcdc_write() function
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