Searched refs:dsim (Results 1 - 8 of 8) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/exynos/
H A Dexynos_mipi_dsi.c65 static int exynos_mipi_regulator_enable(struct mipi_dsim_device *dsim) exynos_mipi_regulator_enable() argument
69 mutex_lock(&dsim->lock); exynos_mipi_regulator_enable()
71 mutex_unlock(&dsim->lock); exynos_mipi_regulator_enable()
76 static int exynos_mipi_regulator_disable(struct mipi_dsim_device *dsim) exynos_mipi_regulator_disable() argument
80 mutex_lock(&dsim->lock); exynos_mipi_regulator_disable()
82 mutex_unlock(&dsim->lock); exynos_mipi_regulator_disable()
88 static void exynos_mipi_update_cfg(struct mipi_dsim_device *dsim) exynos_mipi_update_cfg() argument
95 exynos_mipi_dsi_stand_by(dsim, 0); exynos_mipi_update_cfg()
97 exynos_mipi_dsi_init_dsim(dsim); exynos_mipi_update_cfg()
98 exynos_mipi_dsi_init_link(dsim); exynos_mipi_update_cfg()
100 exynos_mipi_dsi_set_hs_enable(dsim); exynos_mipi_update_cfg()
103 exynos_mipi_dsi_set_display_mode(dsim, dsim->dsim_config); exynos_mipi_update_cfg()
105 exynos_mipi_dsi_init_interrupt(dsim); exynos_mipi_update_cfg()
111 exynos_mipi_dsi_stand_by(dsim, 1); exynos_mipi_update_cfg()
114 static int exynos_mipi_dsi_early_blank_mode(struct mipi_dsim_device *dsim, exynos_mipi_dsi_early_blank_mode() argument
117 struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv; exynos_mipi_dsi_early_blank_mode()
118 struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev; exynos_mipi_dsi_early_blank_mode()
122 if (dsim->suspended) exynos_mipi_dsi_early_blank_mode()
128 clk_disable(dsim->clock); exynos_mipi_dsi_early_blank_mode()
130 exynos_mipi_regulator_disable(dsim); exynos_mipi_dsi_early_blank_mode()
132 dsim->suspended = true; exynos_mipi_dsi_early_blank_mode()
142 static int exynos_mipi_dsi_blank_mode(struct mipi_dsim_device *dsim, int power) exynos_mipi_dsi_blank_mode() argument
144 struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv; exynos_mipi_dsi_blank_mode()
145 struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev; exynos_mipi_dsi_blank_mode()
149 if (!dsim->suspended) exynos_mipi_dsi_blank_mode()
156 exynos_mipi_regulator_enable(dsim); exynos_mipi_dsi_blank_mode()
159 phy_power_on(dsim->phy); exynos_mipi_dsi_blank_mode()
161 clk_enable(dsim->clock); exynos_mipi_dsi_blank_mode()
163 exynos_mipi_update_cfg(dsim); exynos_mipi_dsi_blank_mode()
169 dsim->suspended = false; exynos_mipi_dsi_blank_mode()
268 struct mipi_dsim_device *dsim, exynos_mipi_dsi_bind_lcd_ddi()
276 mutex_lock(&dsim->lock); exynos_mipi_dsi_bind_lcd_ddi()
282 (dsim->id != dsim_ddi->bus_id)) exynos_mipi_dsi_bind_lcd_ddi()
285 dev_dbg(dsim->dev, "lcd_drv->id = %d, lcd_dev->id = %d\n", exynos_mipi_dsi_bind_lcd_ddi()
287 dev_dbg(dsim->dev, "lcd_dev->bus_id = %d, dsim->id = %d\n", exynos_mipi_dsi_bind_lcd_ddi()
288 lcd_dev->bus_id, dsim->id); exynos_mipi_dsi_bind_lcd_ddi()
291 lcd_dev->master = dsim; exynos_mipi_dsi_bind_lcd_ddi()
293 lcd_dev->dev.parent = dsim->dev; exynos_mipi_dsi_bind_lcd_ddi()
298 dev_err(dsim->dev, exynos_mipi_dsi_bind_lcd_ddi()
301 mutex_unlock(&dsim->lock); exynos_mipi_dsi_bind_lcd_ddi()
306 dsim->dsim_lcd_dev = lcd_dev; exynos_mipi_dsi_bind_lcd_ddi()
307 dsim->dsim_lcd_drv = lcd_drv; exynos_mipi_dsi_bind_lcd_ddi()
309 mutex_unlock(&dsim->lock); exynos_mipi_dsi_bind_lcd_ddi()
315 mutex_unlock(&dsim->lock); exynos_mipi_dsi_bind_lcd_ddi()
333 struct mipi_dsim_device *dsim; exynos_mipi_dsi_probe() local
339 dsim = devm_kzalloc(&pdev->dev, sizeof(struct mipi_dsim_device), exynos_mipi_dsi_probe()
341 if (!dsim) { exynos_mipi_dsi_probe()
342 dev_err(&pdev->dev, "failed to allocate dsim object.\n"); exynos_mipi_dsi_probe()
346 dsim->pd = to_dsim_plat(pdev); exynos_mipi_dsi_probe()
347 dsim->dev = &pdev->dev; exynos_mipi_dsi_probe()
348 dsim->id = pdev->id; exynos_mipi_dsi_probe()
351 dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd; exynos_mipi_dsi_probe()
353 dev_err(&pdev->dev, "failed to get platform data for dsim.\n"); exynos_mipi_dsi_probe()
359 dev_err(&pdev->dev, "failed to get dsim config data.\n"); exynos_mipi_dsi_probe()
363 dsim->dsim_config = dsim_config; exynos_mipi_dsi_probe()
364 dsim->master_ops = &master_ops; exynos_mipi_dsi_probe()
366 mutex_init(&dsim->lock); exynos_mipi_dsi_probe()
375 dsim->phy = devm_phy_get(&pdev->dev, "dsim"); exynos_mipi_dsi_probe()
376 if (IS_ERR(dsim->phy)) exynos_mipi_dsi_probe()
377 return PTR_ERR(dsim->phy); exynos_mipi_dsi_probe()
379 dsim->clock = devm_clk_get(&pdev->dev, "dsim0"); exynos_mipi_dsi_probe()
380 if (IS_ERR(dsim->clock)) { exynos_mipi_dsi_probe()
381 dev_err(&pdev->dev, "failed to get dsim clock source\n"); exynos_mipi_dsi_probe()
385 clk_enable(dsim->clock); exynos_mipi_dsi_probe()
389 dsim->reg_base = devm_ioremap_resource(&pdev->dev, res); exynos_mipi_dsi_probe()
390 if (IS_ERR(dsim->reg_base)) { exynos_mipi_dsi_probe()
391 ret = PTR_ERR(dsim->reg_base); exynos_mipi_dsi_probe()
395 mutex_init(&dsim->lock); exynos_mipi_dsi_probe()
398 dsim_ddi = exynos_mipi_dsi_bind_lcd_ddi(dsim, dsim_pd->lcd_panel_name); exynos_mipi_dsi_probe()
405 dsim->irq = platform_get_irq(pdev, 0); exynos_mipi_dsi_probe()
406 if (IS_ERR_VALUE(dsim->irq)) { exynos_mipi_dsi_probe()
407 dev_err(&pdev->dev, "failed to request dsim irq resource\n"); exynos_mipi_dsi_probe()
414 platform_set_drvdata(pdev, dsim); exynos_mipi_dsi_probe()
416 ret = devm_request_irq(&pdev->dev, dsim->irq, exynos_mipi_dsi_probe()
418 IRQF_SHARED, dev_name(&pdev->dev), dsim); exynos_mipi_dsi_probe()
420 dev_err(&pdev->dev, "failed to request dsim irq\n"); exynos_mipi_dsi_probe()
426 exynos_mipi_dsi_init_interrupt(dsim); exynos_mipi_dsi_probe()
434 exynos_mipi_regulator_enable(dsim); exynos_mipi_dsi_probe()
442 exynos_mipi_regulator_enable(dsim); exynos_mipi_dsi_probe()
445 phy_power_on(dsim->phy); exynos_mipi_dsi_probe()
447 exynos_mipi_update_cfg(dsim); exynos_mipi_dsi_probe()
453 dsim->suspended = false; exynos_mipi_dsi_probe()
456 platform_set_drvdata(pdev, dsim); exynos_mipi_dsi_probe()
464 clk_disable(dsim->clock); exynos_mipi_dsi_probe()
470 struct mipi_dsim_device *dsim = platform_get_drvdata(pdev); exynos_mipi_dsi_remove() local
474 clk_disable(dsim->clock); exynos_mipi_dsi_remove()
478 if (dsim->id != dsim_ddi->bus_id) exynos_mipi_dsi_remove()
497 struct mipi_dsim_device *dsim = platform_get_drvdata(pdev); exynos_mipi_dsi_suspend() local
498 struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv; exynos_mipi_dsi_suspend()
499 struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev; exynos_mipi_dsi_suspend()
501 disable_irq(dsim->irq); exynos_mipi_dsi_suspend()
503 if (dsim->suspended) exynos_mipi_dsi_suspend()
510 phy_power_off(dsim->phy); exynos_mipi_dsi_suspend()
512 clk_disable(dsim->clock); exynos_mipi_dsi_suspend()
514 exynos_mipi_regulator_disable(dsim); exynos_mipi_dsi_suspend()
516 dsim->suspended = true; exynos_mipi_dsi_suspend()
524 struct mipi_dsim_device *dsim = platform_get_drvdata(pdev); exynos_mipi_dsi_resume() local
525 struct mipi_dsim_lcd_driver *client_drv = dsim->dsim_lcd_drv; exynos_mipi_dsi_resume()
526 struct mipi_dsim_lcd_device *client_dev = dsim->dsim_lcd_dev; exynos_mipi_dsi_resume()
528 enable_irq(dsim->irq); exynos_mipi_dsi_resume()
530 if (!dsim->suspended) exynos_mipi_dsi_resume()
537 exynos_mipi_regulator_enable(dsim); exynos_mipi_dsi_resume()
540 phy_power_on(dsim->phy); exynos_mipi_dsi_resume()
542 clk_enable(dsim->clock); exynos_mipi_dsi_resume()
544 exynos_mipi_update_cfg(dsim); exynos_mipi_dsi_resume()
550 dsim->suspended = false; exynos_mipi_dsi_resume()
564 .name = "exynos-mipi-dsim",
267 exynos_mipi_dsi_bind_lcd_ddi( struct mipi_dsim_device *dsim, const char *name) exynos_mipi_dsi_bind_lcd_ddi() argument
H A Dexynos_mipi_dsi_lowlevel.h18 void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim);
19 void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim);
20 void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim);
21 int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim);
22 void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim,
24 void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
26 void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim,
28 void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
30 void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim,
32 void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim,
34 void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim,
36 void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim,
38 void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim,
40 void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim,
42 void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim,
44 void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim);
45 void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim,
47 void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim,
49 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
51 void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable,
53 void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim,
55 void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p,
57 void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim,
59 void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim,
62 void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim,
64 void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim,
66 void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim,
68 void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim,
70 void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim,
72 void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim,
74 void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim,
76 unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim);
77 void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim,
79 void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim,
81 void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim,
83 void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim,
85 void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim,
87 void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim,
89 void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim,
91 void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim,
93 void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep);
94 unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim);
95 unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim);
96 void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim,
98 void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim,
100 unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim);
101 unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim);
102 unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
103 void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
104 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, unsigned int di,
106 void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim,
108 void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim,
110 unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim);
H A Dexynos_mipi_dsi_lowlevel.c32 void exynos_mipi_dsi_func_reset(struct mipi_dsim_device *dsim) exynos_mipi_dsi_func_reset() argument
36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_func_reset()
40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_func_reset()
43 void exynos_mipi_dsi_sw_reset(struct mipi_dsim_device *dsim) exynos_mipi_dsi_sw_reset() argument
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_sw_reset()
51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_sw_reset()
54 void exynos_mipi_dsi_sw_reset_release(struct mipi_dsim_device *dsim) exynos_mipi_dsi_sw_reset_release() argument
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_sw_reset_release()
62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_sw_reset_release()
65 int exynos_mipi_dsi_get_sw_reset_release(struct mipi_dsim_device *dsim) exynos_mipi_dsi_get_sw_reset_release() argument
67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) & exynos_mipi_dsi_get_sw_reset_release()
71 unsigned int exynos_mipi_dsi_read_interrupt_mask(struct mipi_dsim_device *dsim) exynos_mipi_dsi_read_interrupt_mask() argument
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK); exynos_mipi_dsi_read_interrupt_mask()
80 void exynos_mipi_dsi_set_interrupt_mask(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_interrupt_mask() argument
90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); exynos_mipi_dsi_set_interrupt_mask()
93 void exynos_mipi_dsi_init_fifo_pointer(struct mipi_dsim_device *dsim, exynos_mipi_dsi_init_fifo_pointer() argument
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
110 void exynos_mipi_dsi_set_phy_tunning(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_phy_tunning() argument
113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_set_phy_tunning()
116 void exynos_mipi_dsi_set_main_stand_by(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_main_stand_by() argument
121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_stand_by()
128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_stand_by()
131 void exynos_mipi_dsi_set_main_disp_resol(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_main_disp_resol() argument
137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) & exynos_mipi_dsi_set_main_disp_resol()
139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_disp_resol()
145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_disp_resol()
148 void exynos_mipi_dsi_set_main_disp_vporch(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_main_disp_vporch() argument
153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) & exynos_mipi_dsi_set_main_disp_vporch()
161 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH); exynos_mipi_dsi_set_main_disp_vporch()
164 void exynos_mipi_dsi_set_main_disp_hporch(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_main_disp_hporch() argument
169 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MHPORCH)) & exynos_mipi_dsi_set_main_disp_hporch()
174 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH); exynos_mipi_dsi_set_main_disp_hporch()
177 void exynos_mipi_dsi_set_main_disp_sync_area(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_main_disp_sync_area() argument
182 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MSYNC)) & exynos_mipi_dsi_set_main_disp_sync_area()
188 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC); exynos_mipi_dsi_set_main_disp_sync_area()
191 void exynos_mipi_dsi_set_sub_disp_resol(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_sub_disp_resol() argument
196 reg = (readl(dsim->reg_base + EXYNOS_DSIM_SDRESOL)) & exynos_mipi_dsi_set_sub_disp_resol()
199 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
204 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
207 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
210 void exynos_mipi_dsi_init_config(struct mipi_dsim_device *dsim) exynos_mipi_dsi_init_config() argument
212 struct mipi_dsim_config *dsim_config = dsim->dsim_config; exynos_mipi_dsi_init_config()
214 unsigned int cfg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & exynos_mipi_dsi_init_config()
226 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_init_config()
229 void exynos_mipi_dsi_display_config(struct mipi_dsim_device *dsim, exynos_mipi_dsi_display_config() argument
232 u32 reg = (readl(dsim->reg_base + EXYNOS_DSIM_CONFIG)) & exynos_mipi_dsi_display_config()
241 dev_err(dsim->dev, "unknown lcd type.\n"); exynos_mipi_dsi_display_config()
250 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_display_config()
253 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, exynos_mipi_dsi_enable_lane() argument
258 reg = readl(dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_enable_lane()
265 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_enable_lane()
269 void exynos_mipi_dsi_set_data_lane_number(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_data_lane_number() argument
277 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_set_data_lane_number()
280 void exynos_mipi_dsi_enable_afc(struct mipi_dsim_device *dsim, unsigned int enable, exynos_mipi_dsi_enable_afc() argument
283 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_enable_afc()
292 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_enable_afc()
295 void exynos_mipi_dsi_enable_pll_bypass(struct mipi_dsim_device *dsim, exynos_mipi_dsi_enable_pll_bypass() argument
298 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_enable_pll_bypass()
303 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_pll_bypass()
306 void exynos_mipi_dsi_set_pll_pms(struct mipi_dsim_device *dsim, unsigned int p, exynos_mipi_dsi_set_pll_pms() argument
309 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_set_pll_pms()
313 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_set_pll_pms()
316 void exynos_mipi_dsi_pll_freq_band(struct mipi_dsim_device *dsim, exynos_mipi_dsi_pll_freq_band() argument
319 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_pll_freq_band()
324 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_pll_freq_band()
327 void exynos_mipi_dsi_pll_freq(struct mipi_dsim_device *dsim, exynos_mipi_dsi_pll_freq() argument
331 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_pll_freq()
337 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_pll_freq()
340 void exynos_mipi_dsi_pll_stable_time(struct mipi_dsim_device *dsim, exynos_mipi_dsi_pll_stable_time() argument
343 writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR); exynos_mipi_dsi_pll_stable_time()
346 void exynos_mipi_dsi_enable_pll(struct mipi_dsim_device *dsim, unsigned int enable) exynos_mipi_dsi_enable_pll() argument
348 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_enable_pll()
353 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_enable_pll()
356 void exynos_mipi_dsi_set_byte_clock_src(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_byte_clock_src() argument
359 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_set_byte_clock_src()
364 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_set_byte_clock_src()
367 void exynos_mipi_dsi_enable_byte_clock(struct mipi_dsim_device *dsim, exynos_mipi_dsi_enable_byte_clock() argument
370 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_enable_byte_clock()
375 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_byte_clock()
378 void exynos_mipi_dsi_set_esc_clk_prs(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_esc_clk_prs() argument
381 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_set_esc_clk_prs()
388 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_set_esc_clk_prs()
391 void exynos_mipi_dsi_enable_esc_clk_on_lane(struct mipi_dsim_device *dsim, exynos_mipi_dsi_enable_esc_clk_on_lane() argument
394 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_esc_clk_on_lane()
402 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_esc_clk_on_lane()
405 void exynos_mipi_dsi_force_dphy_stop_state(struct mipi_dsim_device *dsim, exynos_mipi_dsi_force_dphy_stop_state() argument
408 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & exynos_mipi_dsi_force_dphy_stop_state()
413 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_force_dphy_stop_state()
416 unsigned int exynos_mipi_dsi_is_lane_state(struct mipi_dsim_device *dsim) exynos_mipi_dsi_is_lane_state() argument
418 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); exynos_mipi_dsi_is_lane_state()
434 void exynos_mipi_dsi_set_stop_state_counter(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_stop_state_counter() argument
437 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE)) & exynos_mipi_dsi_set_stop_state_counter()
442 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_stop_state_counter()
445 void exynos_mipi_dsi_set_bta_timeout(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_bta_timeout() argument
448 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & exynos_mipi_dsi_set_bta_timeout()
453 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); exynos_mipi_dsi_set_bta_timeout()
456 void exynos_mipi_dsi_set_lpdr_timeout(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_lpdr_timeout() argument
459 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_TIMEOUT)) & exynos_mipi_dsi_set_lpdr_timeout()
464 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); exynos_mipi_dsi_set_lpdr_timeout()
467 void exynos_mipi_dsi_set_cpu_transfer_mode(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_cpu_transfer_mode() argument
470 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_cpu_transfer_mode()
477 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_cpu_transfer_mode()
480 void exynos_mipi_dsi_set_lcdc_transfer_mode(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_lcdc_transfer_mode() argument
483 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_lcdc_transfer_mode()
490 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_lcdc_transfer_mode()
493 void exynos_mipi_dsi_enable_hs_clock(struct mipi_dsim_device *dsim, exynos_mipi_dsi_enable_hs_clock() argument
496 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_CLKCTRL)) & exynos_mipi_dsi_enable_hs_clock()
501 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_hs_clock()
504 void exynos_mipi_dsi_dp_dn_swap(struct mipi_dsim_device *dsim, exynos_mipi_dsi_dp_dn_swap() argument
507 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); exynos_mipi_dsi_dp_dn_swap()
512 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); exynos_mipi_dsi_dp_dn_swap()
515 void exynos_mipi_dsi_hs_zero_ctrl(struct mipi_dsim_device *dsim, exynos_mipi_dsi_hs_zero_ctrl() argument
518 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_hs_zero_ctrl()
523 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_hs_zero_ctrl()
526 void exynos_mipi_dsi_prep_ctrl(struct mipi_dsim_device *dsim, unsigned int prep) exynos_mipi_dsi_prep_ctrl() argument
528 unsigned int reg = (readl(dsim->reg_base + EXYNOS_DSIM_PLLCTRL)) & exynos_mipi_dsi_prep_ctrl()
533 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_prep_ctrl()
536 unsigned int exynos_mipi_dsi_read_interrupt(struct mipi_dsim_device *dsim) exynos_mipi_dsi_read_interrupt() argument
538 return readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_read_interrupt()
541 void exynos_mipi_dsi_clear_interrupt(struct mipi_dsim_device *dsim, exynos_mipi_dsi_clear_interrupt() argument
544 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_clear_interrupt()
548 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_clear_interrupt()
551 void exynos_mipi_dsi_set_interrupt(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_interrupt() argument
561 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_set_interrupt()
564 unsigned int exynos_mipi_dsi_is_pll_stable(struct mipi_dsim_device *dsim) exynos_mipi_dsi_is_pll_stable() argument
568 reg = readl(dsim->reg_base + EXYNOS_DSIM_STATUS); exynos_mipi_dsi_is_pll_stable()
573 unsigned int exynos_mipi_dsi_get_fifo_state(struct mipi_dsim_device *dsim) exynos_mipi_dsi_get_fifo_state() argument
575 return readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL) & ~(0x1f); exynos_mipi_dsi_get_fifo_state()
578 void exynos_mipi_dsi_wr_tx_header(struct mipi_dsim_device *dsim, exynos_mipi_dsi_wr_tx_header() argument
583 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); exynos_mipi_dsi_wr_tx_header()
586 void exynos_mipi_dsi_rd_tx_header(struct mipi_dsim_device *dsim, exynos_mipi_dsi_rd_tx_header() argument
591 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); exynos_mipi_dsi_rd_tx_header()
594 unsigned int exynos_mipi_dsi_rd_rx_fifo(struct mipi_dsim_device *dsim) exynos_mipi_dsi_rd_rx_fifo() argument
596 return readl(dsim->reg_base + EXYNOS_DSIM_RXFIFO); exynos_mipi_dsi_rd_rx_fifo()
599 unsigned int _exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) _exynos_mipi_dsi_get_frame_done_status() argument
601 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); _exynos_mipi_dsi_get_frame_done_status()
606 void _exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) _exynos_mipi_dsi_clear_frame_done() argument
608 unsigned int reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC); _exynos_mipi_dsi_clear_frame_done()
610 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + _exynos_mipi_dsi_clear_frame_done()
614 void exynos_mipi_dsi_wr_tx_data(struct mipi_dsim_device *dsim, exynos_mipi_dsi_wr_tx_data() argument
617 writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD); exynos_mipi_dsi_wr_tx_data()
H A Dexynos_mipi_dsi_common.c78 struct mipi_dsim_device *dsim = dev_id; exynos_mipi_dsi_interrupt_handler() local
81 intsrc = exynos_mipi_dsi_read_interrupt(dsim); exynos_mipi_dsi_interrupt_handler()
82 intmsk = exynos_mipi_dsi_read_interrupt_mask(dsim); exynos_mipi_dsi_interrupt_handler()
87 dev_dbg(dsim->dev, "MIPI INTMSK_RX_DONE\n"); exynos_mipi_dsi_interrupt_handler()
91 dev_dbg(dsim->dev, "MIPI INTMSK_FIFO_EMPTY\n"); exynos_mipi_dsi_interrupt_handler()
94 exynos_mipi_dsi_clear_interrupt(dsim, intmsk); exynos_mipi_dsi_interrupt_handler()
101 * @dsim: mipi dsim device structure.
105 static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim, exynos_mipi_dsi_long_data_wr() argument
121 dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n", exynos_mipi_dsi_long_data_wr()
128 dev_dbg(dsim->dev, exynos_mipi_dsi_long_data_wr()
136 exynos_mipi_dsi_wr_tx_data(dsim, payload); exynos_mipi_dsi_long_data_wr()
144 dev_dbg(dsim->dev, exynos_mipi_dsi_long_data_wr()
151 exynos_mipi_dsi_wr_tx_data(dsim, payload); exynos_mipi_dsi_long_data_wr()
156 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id, exynos_mipi_dsi_wr_data() argument
161 if (dsim->state == DSIM_STATE_ULPS) { exynos_mipi_dsi_wr_data()
162 dev_err(dsim->dev, "state is ULPS.\n"); exynos_mipi_dsi_wr_data()
170 mutex_lock(&dsim->lock); exynos_mipi_dsi_wr_data()
180 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); exynos_mipi_dsi_wr_data()
183 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
186 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
195 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]); exynos_mipi_dsi_wr_data()
198 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
201 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
211 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
217 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
233 exynos_mipi_dsi_wr_tx_data(dsim, payload); exynos_mipi_dsi_wr_data()
235 dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n", exynos_mipi_dsi_wr_data()
241 exynos_mipi_dsi_long_data_wr(dsim, data0, data_size); exynos_mipi_dsi_wr_data()
244 exynos_mipi_dsi_wr_tx_header(dsim, data_id, data_size & 0xff, exynos_mipi_dsi_wr_data()
249 dev_warn(dsim->dev, "command write timeout.\n"); exynos_mipi_dsi_wr_data()
250 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
256 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
259 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
271 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
274 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
278 dev_warn(dsim->dev, exynos_mipi_dsi_wr_data()
282 mutex_unlock(&dsim->lock); exynos_mipi_dsi_wr_data()
287 static unsigned int exynos_mipi_dsi_long_data_rd(struct mipi_dsim_device *dsim, exynos_mipi_dsi_long_data_rd() argument
295 dev_dbg(dsim->dev, "mipi dsi rx size : %d\n", rxsize); exynos_mipi_dsi_long_data_rd()
297 dev_dbg(dsim->dev, exynos_mipi_dsi_long_data_rd()
304 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim); exynos_mipi_dsi_long_data_rd()
305 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt); exynos_mipi_dsi_long_data_rd()
309 dev_dbg(dsim->dev, "received value : %02x\n", exynos_mipi_dsi_long_data_rd()
314 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim); exynos_mipi_dsi_long_data_rd()
315 dev_dbg(dsim->dev, "received pkt : %08x\n", rcv_pkt); exynos_mipi_dsi_long_data_rd()
319 dev_dbg(dsim->dev, "received value : %02x\n", exynos_mipi_dsi_long_data_rd()
342 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id, exynos_mipi_dsi_rd_data() argument
349 if (dsim->state == DSIM_STATE_ULPS) { exynos_mipi_dsi_rd_data()
350 dev_err(dsim->dev, "state is ULPS.\n"); exynos_mipi_dsi_rd_data()
358 mutex_lock(&dsim->lock); exynos_mipi_dsi_rd_data()
360 exynos_mipi_dsi_rd_tx_header(dsim, exynos_mipi_dsi_rd_data()
370 exynos_mipi_dsi_rd_tx_header(dsim, exynos_mipi_dsi_rd_data()
375 dev_warn(dsim->dev, exynos_mipi_dsi_rd_data()
379 mutex_unlock(&dsim->lock); exynos_mipi_dsi_rd_data()
386 mutex_unlock(&dsim->lock); exynos_mipi_dsi_rd_data()
392 rx_data = exynos_mipi_dsi_rd_rx_fifo(dsim); exynos_mipi_dsi_rd_data()
408 rxsize = exynos_mipi_dsi_long_data_rd(dsim, req_size, rx_data, exynos_mipi_dsi_rd_data()
414 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim); exynos_mipi_dsi_rd_data()
419 dev_info(dsim->dev, exynos_mipi_dsi_rd_data()
424 mutex_unlock(&dsim->lock); exynos_mipi_dsi_rd_data()
431 rcv_pkt = exynos_mipi_dsi_rd_rx_fifo(dsim); exynos_mipi_dsi_rd_data()
435 dev_dbg(dsim->dev, exynos_mipi_dsi_rd_data()
439 dev_info(dsim->dev, exynos_mipi_dsi_rd_data()
442 mutex_unlock(&dsim->lock); exynos_mipi_dsi_rd_data()
447 static int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, exynos_mipi_dsi_pll_on() argument
455 exynos_mipi_dsi_enable_pll(dsim, 1); exynos_mipi_dsi_pll_on()
458 if (exynos_mipi_dsi_is_pll_stable(dsim)) exynos_mipi_dsi_pll_on()
464 exynos_mipi_dsi_enable_pll(dsim, 0); exynos_mipi_dsi_pll_on()
469 static unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim, exynos_mipi_dsi_change_pll() argument
499 dev_warn(dsim->dev, "fin_pll range should be 6MHz ~ 12MHz\n"); exynos_mipi_dsi_change_pll()
500 exynos_mipi_dsi_enable_afc(dsim, 0, 0); exynos_mipi_dsi_change_pll()
503 exynos_mipi_dsi_enable_afc(dsim, 1, 0x1); exynos_mipi_dsi_change_pll()
505 exynos_mipi_dsi_enable_afc(dsim, 1, 0x0); exynos_mipi_dsi_change_pll()
507 exynos_mipi_dsi_enable_afc(dsim, 1, 0x3); exynos_mipi_dsi_change_pll()
509 exynos_mipi_dsi_enable_afc(dsim, 1, 0x2); exynos_mipi_dsi_change_pll()
511 exynos_mipi_dsi_enable_afc(dsim, 1, 0x5); exynos_mipi_dsi_change_pll()
513 exynos_mipi_dsi_enable_afc(dsim, 1, 0x4); exynos_mipi_dsi_change_pll()
517 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n", exynos_mipi_dsi_change_pll()
520 dev_warn(dsim->dev, "fvco range should be 500MHz ~ 1000MHz\n"); exynos_mipi_dsi_change_pll()
523 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n", exynos_mipi_dsi_change_pll()
533 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band); exynos_mipi_dsi_change_pll()
535 exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler); exynos_mipi_dsi_change_pll()
537 exynos_mipi_dsi_hs_zero_ctrl(dsim, 0); exynos_mipi_dsi_change_pll()
538 exynos_mipi_dsi_prep_ctrl(dsim, 0); exynos_mipi_dsi_change_pll()
541 exynos_mipi_dsi_pll_freq_band(dsim, freq_band); exynos_mipi_dsi_change_pll()
544 exynos_mipi_dsi_pll_stable_time(dsim, dsim->dsim_config->pll_stable_time); exynos_mipi_dsi_change_pll()
547 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n", exynos_mipi_dsi_change_pll()
553 static int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_clock() argument
561 dsim->e_clk_src = byte_clk_sel; exynos_mipi_dsi_set_clock()
564 exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel); exynos_mipi_dsi_set_clock()
568 hs_clk = exynos_mipi_dsi_change_pll(dsim, exynos_mipi_dsi_set_clock()
569 dsim->dsim_config->p, dsim->dsim_config->m, exynos_mipi_dsi_set_clock()
570 dsim->dsim_config->s); exynos_mipi_dsi_set_clock()
572 dev_err(dsim->dev, exynos_mipi_dsi_set_clock()
578 exynos_mipi_dsi_enable_pll_bypass(dsim, 0); exynos_mipi_dsi_set_clock()
579 exynos_mipi_dsi_pll_on(dsim, 1); exynos_mipi_dsi_set_clock()
582 dev_warn(dsim->dev, "this project is not support\n"); exynos_mipi_dsi_set_clock()
583 dev_warn(dsim->dev, exynos_mipi_dsi_set_clock()
586 dev_warn(dsim->dev, "this project is not support\n"); exynos_mipi_dsi_set_clock()
587 dev_warn(dsim->dev, exynos_mipi_dsi_set_clock()
592 esc_div = byte_clk / (dsim->dsim_config->esc_clk); exynos_mipi_dsi_set_clock()
593 dev_dbg(dsim->dev, exynos_mipi_dsi_set_clock()
595 esc_div, byte_clk, dsim->dsim_config->esc_clk); exynos_mipi_dsi_set_clock()
598 dsim->dsim_config->esc_clk) exynos_mipi_dsi_set_clock()
602 dev_dbg(dsim->dev, exynos_mipi_dsi_set_clock()
607 exynos_mipi_dsi_enable_byte_clock(dsim, 1); exynos_mipi_dsi_set_clock()
610 exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div); exynos_mipi_dsi_set_clock()
612 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim, exynos_mipi_dsi_set_clock()
613 (DSIM_LANE_CLOCK | dsim->data_lane), 1); exynos_mipi_dsi_set_clock()
615 dev_dbg(dsim->dev, "byte clock is %luMHz\n", exynos_mipi_dsi_set_clock()
617 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n", exynos_mipi_dsi_set_clock()
618 (dsim->dsim_config->esc_clk / MHZ)); exynos_mipi_dsi_set_clock()
619 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div); exynos_mipi_dsi_set_clock()
620 dev_dbg(dsim->dev, "escape clock is %luMHz\n", exynos_mipi_dsi_set_clock()
626 dev_warn(dsim->dev, "error rate is %lu over.\n", exynos_mipi_dsi_set_clock()
631 dev_warn(dsim->dev, "error rate is %lu under.\n", exynos_mipi_dsi_set_clock()
635 exynos_mipi_dsi_enable_esc_clk_on_lane(dsim, exynos_mipi_dsi_set_clock()
636 (DSIM_LANE_CLOCK | dsim->data_lane), 0); exynos_mipi_dsi_set_clock()
637 exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0); exynos_mipi_dsi_set_clock()
640 exynos_mipi_dsi_enable_byte_clock(dsim, 0); exynos_mipi_dsi_set_clock()
643 exynos_mipi_dsi_pll_on(dsim, 0); exynos_mipi_dsi_set_clock()
649 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim) exynos_mipi_dsi_init_dsim() argument
651 dsim->state = DSIM_STATE_INIT; exynos_mipi_dsi_init_dsim()
653 switch (dsim->dsim_config->e_no_data_lane) { exynos_mipi_dsi_init_dsim()
655 dsim->data_lane = DSIM_LANE_DATA0; exynos_mipi_dsi_init_dsim()
658 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1; exynos_mipi_dsi_init_dsim()
661 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | exynos_mipi_dsi_init_dsim()
665 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 | exynos_mipi_dsi_init_dsim()
669 dev_info(dsim->dev, "data lane is invalid.\n"); exynos_mipi_dsi_init_dsim()
673 exynos_mipi_dsi_sw_reset(dsim); exynos_mipi_dsi_init_dsim()
674 exynos_mipi_dsi_func_reset(dsim); exynos_mipi_dsi_init_dsim()
676 exynos_mipi_dsi_dp_dn_swap(dsim, 0); exynos_mipi_dsi_init_dsim()
681 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim) exynos_mipi_dsi_init_interrupt() argument
686 exynos_mipi_dsi_set_interrupt(dsim, src, 1); exynos_mipi_dsi_init_interrupt()
690 exynos_mipi_dsi_set_interrupt_mask(dsim, src, 1); exynos_mipi_dsi_init_interrupt()
693 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim, exynos_mipi_dsi_enable_frame_done_int() argument
697 exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable); exynos_mipi_dsi_enable_frame_done_int()
702 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim, exynos_mipi_dsi_stand_by() argument
708 exynos_mipi_dsi_set_main_stand_by(dsim, enable); exynos_mipi_dsi_stand_by()
711 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_display_mode() argument
717 dsim_pd = (struct mipi_dsim_platform_data *)dsim->pd; exynos_mipi_dsi_set_display_mode()
723 exynos_mipi_dsi_set_main_disp_vporch(dsim, exynos_mipi_dsi_set_display_mode()
727 exynos_mipi_dsi_set_main_disp_hporch(dsim, exynos_mipi_dsi_set_display_mode()
730 exynos_mipi_dsi_set_main_disp_sync_area(dsim, exynos_mipi_dsi_set_display_mode()
736 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres, exynos_mipi_dsi_set_display_mode()
739 exynos_mipi_dsi_display_config(dsim, dsim_config); exynos_mipi_dsi_set_display_mode()
741 dev_info(dsim->dev, "lcd panel ==> width = %d, height = %d\n", exynos_mipi_dsi_set_display_mode()
747 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim) exynos_mipi_dsi_init_link() argument
751 switch (dsim->state) { exynos_mipi_dsi_init_link()
753 exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f); exynos_mipi_dsi_init_link()
756 exynos_mipi_dsi_init_config(dsim); exynos_mipi_dsi_init_link()
757 exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1); exynos_mipi_dsi_init_link()
758 exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1); exynos_mipi_dsi_init_link()
761 exynos_mipi_dsi_set_clock(dsim, dsim->dsim_config->e_byte_clk, 1); exynos_mipi_dsi_init_link()
764 while (!(exynos_mipi_dsi_is_lane_state(dsim))) { exynos_mipi_dsi_init_link()
767 dev_err(dsim->dev, exynos_mipi_dsi_init_link()
769 dev_err(dsim->dev, exynos_mipi_dsi_init_link()
776 dev_info(dsim->dev, exynos_mipi_dsi_init_link()
778 dev_info(dsim->dev, "DSI Master state is stop state\n"); exynos_mipi_dsi_init_link()
781 dsim->state = DSIM_STATE_STOP; exynos_mipi_dsi_init_link()
784 exynos_mipi_dsi_set_stop_state_counter(dsim, exynos_mipi_dsi_init_link()
785 dsim->dsim_config->stop_holding_cnt); exynos_mipi_dsi_init_link()
786 exynos_mipi_dsi_set_bta_timeout(dsim, exynos_mipi_dsi_init_link()
787 dsim->dsim_config->bta_timeout); exynos_mipi_dsi_init_link()
788 exynos_mipi_dsi_set_lpdr_timeout(dsim, exynos_mipi_dsi_init_link()
789 dsim->dsim_config->rx_timeout); exynos_mipi_dsi_init_link()
793 dev_info(dsim->dev, "DSI Master is already init.\n"); exynos_mipi_dsi_init_link()
800 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim) exynos_mipi_dsi_set_hs_enable() argument
802 if (dsim->state != DSIM_STATE_STOP) { exynos_mipi_dsi_set_hs_enable()
803 dev_warn(dsim->dev, "DSIM is not in stop state.\n"); exynos_mipi_dsi_set_hs_enable()
807 if (dsim->e_clk_src == DSIM_EXT_CLK_BYPASS) { exynos_mipi_dsi_set_hs_enable()
808 dev_warn(dsim->dev, "clock source is external bypass.\n"); exynos_mipi_dsi_set_hs_enable()
812 dsim->state = DSIM_STATE_HSCLKEN; exynos_mipi_dsi_set_hs_enable()
815 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); exynos_mipi_dsi_set_hs_enable()
816 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0); exynos_mipi_dsi_set_hs_enable()
817 exynos_mipi_dsi_enable_hs_clock(dsim, 1); exynos_mipi_dsi_set_hs_enable()
822 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim, exynos_mipi_dsi_set_data_transfer_mode() argument
826 if (dsim->state != DSIM_STATE_HSCLKEN) { exynos_mipi_dsi_set_data_transfer_mode()
827 dev_err(dsim->dev, "HS Clock lane is not enabled.\n"); exynos_mipi_dsi_set_data_transfer_mode()
831 exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0); exynos_mipi_dsi_set_data_transfer_mode()
833 if (dsim->state == DSIM_STATE_INIT || dsim->state == exynos_mipi_dsi_set_data_transfer_mode()
835 dev_err(dsim->dev, exynos_mipi_dsi_set_data_transfer_mode()
840 exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0); exynos_mipi_dsi_set_data_transfer_mode()
846 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim) exynos_mipi_dsi_get_frame_done_status() argument
848 return _exynos_mipi_dsi_get_frame_done_status(dsim); exynos_mipi_dsi_get_frame_done_status()
851 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim) exynos_mipi_dsi_clear_frame_done() argument
853 _exynos_mipi_dsi_clear_frame_done(dsim); exynos_mipi_dsi_clear_frame_done()
858 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim, exynos_mipi_dsi_fifo_clear() argument
863 exynos_mipi_dsi_sw_reset_release(dsim); exynos_mipi_dsi_fifo_clear()
864 exynos_mipi_dsi_func_reset(dsim); exynos_mipi_dsi_fifo_clear()
867 if (exynos_mipi_dsi_get_sw_reset_release(dsim)) { exynos_mipi_dsi_fifo_clear()
868 exynos_mipi_dsi_init_interrupt(dsim); exynos_mipi_dsi_fifo_clear()
869 dev_dbg(dsim->dev, "reset release done.\n"); exynos_mipi_dsi_fifo_clear()
874 dev_err(dsim->dev, "failed to clear dsim fifo.\n"); exynos_mipi_dsi_fifo_clear()
H A Dexynos_mipi_dsi_common.h21 int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
23 int exynos_mipi_dsi_rd_data(struct mipi_dsim_device *dsim, unsigned int data_id,
26 void exynos_mipi_dsi_init_interrupt(struct mipi_dsim_device *dsim);
27 int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim);
28 void exynos_mipi_dsi_stand_by(struct mipi_dsim_device *dsim,
30 int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
32 int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim);
33 int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim);
34 int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
36 int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
38 int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim);
39 int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim);
43 int exynos_mipi_dsi_fifo_clear(struct mipi_dsim_device *dsim,
/linux-4.4.14/include/video/
H A Dexynos_mipi_dsim.h282 int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
284 int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
286 int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
287 int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
291 int (*set_early_blank_mode)(struct mipi_dsim_device *dsim, int power);
292 int (*set_blank_mode)(struct mipi_dsim_device *dsim, int power);
/linux-4.4.14/drivers/clk/samsung/
H A Dclk-s5pv210.c679 GATE(CLK_DSIM, "dsim", "dout_pclkd", CLK_GATE_IP1, 2, 0, 0),
/linux-4.4.14/drivers/gpu/drm/exynos/
H A Dexynos_drm_dsi.c1934 dsi->phy = devm_phy_get(dev, "dsim"); exynos_dsi_probe()
1936 dev_info(dev, "failed to get dsim phy\n"); exynos_dsi_probe()

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