Searched refs:dpm_levels (Results 1 – 4 of 4) sorted by relevance
2528 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()2529 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()2587 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()2605 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()2607 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()3261 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()3307 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()3310 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()3352 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()3358 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()[all …]
64 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member
2658 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()2659 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()2717 if (dpm_table->dpm_levels[i-1].enabled) in ci_get_dpm_level_enable_mask_value()2735 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value; in ci_populate_smc_link_level()2737 amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()3400 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()3445 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()3448 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()3488 dpm_table->dpm_levels[i].enabled = false; in ci_reset_single_dpm_table()3494 dpm_table->dpm_levels[index].value = pcie_gen; in ci_setup_pcie_table_entry()[all …]
65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; member