2658 								   pi->dpm_table.sclk_table.dpm_levels[i].value,  in ci_do_program_memory_timing_parameters()
2659 								   pi->dpm_table.mclk_table.dpm_levels[j].value,  in ci_do_program_memory_timing_parameters()
2717 		if (dpm_table->dpm_levels[i-1].enabled)  in ci_get_dpm_level_enable_mask_value()
2735 			(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;  in ci_populate_smc_link_level()
2737 			amdgpu_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);  in ci_populate_smc_link_level()
3400 						       dpm_table->sclk_table.dpm_levels[i].value,  in ci_populate_all_graphic_levels()
3445 		if (dpm_table->mclk_table.dpm_levels[i].value == 0)  in ci_populate_all_memory_levels()
3448 						      dpm_table->mclk_table.dpm_levels[i].value,  in ci_populate_all_memory_levels()
3488 		dpm_table->dpm_levels[i].enabled = false;  in ci_reset_single_dpm_table()
3494 	dpm_table->dpm_levels[index].value = pcie_gen;  in ci_setup_pcie_table_entry()
3495 	dpm_table->dpm_levels[index].param1 = pcie_lanes;  in ci_setup_pcie_table_entry()
3496 	dpm_table->dpm_levels[index].enabled = true;  in ci_setup_pcie_table_entry()
3588 		    (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3590 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =  in ci_setup_default_dpm_tables()
3592 			pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3601 		    (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=  in ci_setup_default_dpm_tables()
3603 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =  in ci_setup_default_dpm_tables()
3605 			pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =  in ci_setup_default_dpm_tables()
3612 		pi->dpm_table.vddc_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3614 		pi->dpm_table.vddc_table.dpm_levels[i].param1 =  in ci_setup_default_dpm_tables()
3616 		pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3623 			pi->dpm_table.vddci_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3625 			pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3633 			pi->dpm_table.mvdd_table.dpm_levels[i].value =  in ci_setup_default_dpm_tables()
3635 			pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;  in ci_setup_default_dpm_tables()
3652 		if (value == table->dpm_levels[i].value) {  in ci_find_boot_level()
3816 		if ((dpm_table->dpm_levels[i].value < low_limit) ||  in ci_trim_single_dpm_states()
3817 		    (dpm_table->dpm_levels[i].value > high_limit))  in ci_trim_single_dpm_states()
3818 			dpm_table->dpm_levels[i].enabled = false;  in ci_trim_single_dpm_states()
3820 			dpm_table->dpm_levels[i].enabled = true;  in ci_trim_single_dpm_states()
3833 		if ((pcie_table->dpm_levels[i].value < speed_low) ||  in ci_trim_pcie_dpm_states()
3834 		    (pcie_table->dpm_levels[i].param1 < lanes_low) ||  in ci_trim_pcie_dpm_states()
3835 		    (pcie_table->dpm_levels[i].value > speed_high) ||  in ci_trim_pcie_dpm_states()
3836 		    (pcie_table->dpm_levels[i].param1 > lanes_high))  in ci_trim_pcie_dpm_states()
3837 			pcie_table->dpm_levels[i].enabled = false;  in ci_trim_pcie_dpm_states()
3839 			pcie_table->dpm_levels[i].enabled = true;  in ci_trim_pcie_dpm_states()
3843 		if (pcie_table->dpm_levels[i].enabled) {  in ci_trim_pcie_dpm_states()
3845 				if (pcie_table->dpm_levels[j].enabled) {  in ci_trim_pcie_dpm_states()
3846 					if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&  in ci_trim_pcie_dpm_states()
3847 					    (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))  in ci_trim_pcie_dpm_states()
3848 						pcie_table->dpm_levels[j].enabled = false;  in ci_trim_pcie_dpm_states()
3977 		if (sclk == sclk_table->dpm_levels[i].value)  in ci_find_dpm_states_clocks_in_dpm_table()
3990 		if (mclk == mclk_table->dpm_levels[i].value)  in ci_find_dpm_states_clocks_in_dpm_table()
4016 		dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4019 		dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4882 						     pi->dpm_table.mclk_table.dpm_levels[i].value,  in ci_convert_mc_reg_table_to_smc()