| /linux-4.4.14/arch/cris/arch-v32/mach-a3/ |
| H A D | dram_init.S | 25 ;; Refer to ddr2 MDS for initialization sequence
33 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
34 move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
43 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
44 move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
45 REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
47 move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
56 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
74 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
79 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
84 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ |
| H A D | ddr2_defs.h | 6 * file: ddr2.r
8 * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
82 /* C-code for register scope ddr2 */
84 /* Register rw_cfg, scope ddr2, type rw */
102 /* Register rw_timing, scope ddr2, type rw */
117 /* Register rw_latency, scope ddr2, type rw */
126 /* Register rw_phy_cfg, scope ddr2, type rw */
134 /* Register rw_phy_ctrl, scope ddr2, type rw */
144 /* Register rw_ctrl, scope ddr2, type rw */
153 /* Register rw_pwr_down, scope ddr2, type rw */
162 /* Register r_stat, scope ddr2, type r */
174 /* Register rw_imp_ctrl, scope ddr2, type rw */
184 /* Register rw_dll_ctrl, scope ddr2, type rw */
194 /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
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| H A D | clkgen_defs.h | 101 unsigned int ddr2 : 1; member in struct:__anon871
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| /linux-4.4.14/arch/mips/ralink/ |
| H A D | rt3883.c | 81 u32 ddr2; ralink_clk_init() local
86 ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2; ralink_clk_init()
91 sys_rate = (ddr2) ? 125000000 : 83000000; ralink_clk_init()
95 sys_rate = (ddr2) ? 128000000 : 96000000; ralink_clk_init()
99 sys_rate = (ddr2) ? 160000000 : 120000000; ralink_clk_init()
103 sys_rate = (ddr2) ? 166000000 : 125000000; ralink_clk_init()
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/ |
| H A D | ddr2_defs_asm.h | 6 * file: ddr2.r
8 * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
53 /* Register rw_cfg, scope ddr2, type rw */
85 /* Register rw_timing, scope ddr2, type rw */
106 /* Register rw_latency, scope ddr2, type rw */
113 /* Register rw_phy_cfg, scope ddr2, type rw */
119 /* Register rw_phy_ctrl, scope ddr2, type rw */
131 /* Register rw_ctrl, scope ddr2, type rw */
138 /* Register rw_pwr_down, scope ddr2, type rw */
146 /* Register r_stat, scope ddr2, type r */
164 /* Register rw_imp_ctrl, scope ddr2, type rw */
172 /* Register rw_dll_ctrl, scope ddr2, type rw */
181 /* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
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| /linux-4.4.14/drivers/cpufreq/ |
| H A D | cris-artpec3-cpufreq.c | 81 REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg); cris_sdram_freq_notifier()
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| /linux-4.4.14/arch/arm/mach-davinci/ |
| H A D | cpuidle.c | 23 #include <mach/ddr2.h>
|
| H A D | sleep.S | 25 #include <mach/ddr2.h>
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| /linux-4.4.14/drivers/edac/ |
| H A D | ppc4xx_edac.c | 90 * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
144 * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
198 .compatible = "ibm,sdram-4xx-ddr2"
662 * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
690 * ibm,sdram-4xx-ddr2 ECC errors.
713 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
744 * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
770 * associated with the ibm,sdram-4xx-ddr2 controller being
808 * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
881 * associated with the ibm,sdram-4xx-ddr2 controller for which
888 * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
1007 * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
1093 * associated with the ibm,sdram-4xx-ddr2 controller for which
1224 * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1348 * with the specified ibm,sdram-4xx-ddr2 controller described by the
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| /linux-4.4.14/arch/mips/include/asm/octeon/ |
| H A D | cvmx-lmcx-defs.h | 1414 uint64_t ddr2:1; member in struct:cvmx_lmcx_ddr2_ctl::cvmx_lmcx_ddr2_ctl_s
1416 uint64_t ddr2:1;
1455 uint64_t ddr2:1; member in struct:cvmx_lmcx_ddr2_ctl::cvmx_lmcx_ddr2_ctl_cn30xx
1457 uint64_t ddr2:1;
|