Searched refs:cntl (Results 1 - 42 of 42) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/
H A Damba-clcd-versatile.c26 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
50 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
75 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
99 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
124 .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
H A Damba-clcd.c97 static void clcdfb_enable(struct clcd_fb *fb, u32 cntl) clcdfb_enable() argument
110 cntl |= CNTL_LCDEN; clcdfb_enable()
111 writel(cntl, fb->regs + fb->off_cntl); clcdfb_enable()
118 cntl |= CNTL_LCDPWR; clcdfb_enable()
119 writel(cntl, fb->regs + fb->off_cntl); clcdfb_enable()
138 caps = fb->panel->cntl & CNTL_BGR ? clcdfb_set_bitfields()
145 if (!(fb->panel->cntl & CNTL_LCDTFT)) clcdfb_set_bitfields()
311 fb->clcd_cntl = regs.cntl; clcdfb_set_par()
313 clcdfb_enable(fb, regs.cntl); clcdfb_set_par()
633 fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1); clcdfb_of_init_tft_panel()
690 fb->panel->cntl |= CNTL_BEBO; clcdfb_of_init_display()
H A Dmacfb.c69 unsigned char cntl; /* a guess as to purpose */ member in struct:__anon11136
249 nubus_writeb(0xFF, &rbv_cmap_regs->cntl); rbv_setpalette()
/linux-4.4.14/arch/arm/mach-omap1/
H A Dtime.c63 u32 cntl; /* CNTL_TIMER, R/W */ member in struct:__anon236
82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); omap_mpu_set_autoreset()
89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); omap_mpu_remove_autoreset()
101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); omap_mpu_timer_start()
105 writel(timerflags, &timer->cntl); omap_mpu_timer_start()
112 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); omap_mpu_timer_stop()
/linux-4.4.14/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_dbgdev.c243 union TCP_WATCH_CNTL_BITS *cntl, dbgdev_address_watch_set_registers()
248 BUG_ON(!adw_info || !addrHi || !addrLo || !cntl); dbgdev_address_watch_set_registers()
253 cntl->u32All = 0; dbgdev_address_watch_set_registers()
256 cntl->bitfields.mask = dbgdev_address_watch_set_registers()
260 cntl->bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; dbgdev_address_watch_set_registers()
269 cntl->bitfields.mode = adw_info->watch_mode[index]; dbgdev_address_watch_set_registers()
270 cntl->bitfields.vmid = (uint32_t) vmid; dbgdev_address_watch_set_registers()
272 cntl->u32All |= ADDRESS_WATCH_REG_CNTL_ATC_BIT; dbgdev_address_watch_set_registers()
274 pr_debug("\t\t%20s %08x\n", "set reg mask :", cntl->bitfields.mask); dbgdev_address_watch_set_registers()
286 union TCP_WATCH_CNTL_BITS cntl; dbgdev_address_watch_nodiq() local
302 cntl.u32All = 0; dbgdev_address_watch_nodiq()
318 &cntl, i, pdd->qpd.vmid); dbgdev_address_watch_nodiq()
330 cntl.bitfields.mask); dbgdev_address_watch_nodiq()
332 cntl.bitfields.mode); dbgdev_address_watch_nodiq()
334 cntl.bitfields.vmid); dbgdev_address_watch_nodiq()
336 cntl.bitfields.atc); dbgdev_address_watch_nodiq()
342 cntl.u32All, dbgdev_address_watch_nodiq()
356 union TCP_WATCH_CNTL_BITS cntl; dbgdev_address_watch_diq() local
370 cntl.u32All = 0; dbgdev_address_watch_diq()
414 &cntl, dbgdev_address_watch_diq()
430 cntl.bitfields.mask); dbgdev_address_watch_diq()
432 cntl.bitfields.mode); dbgdev_address_watch_diq()
434 cntl.bitfields.vmid); dbgdev_address_watch_diq()
436 cntl.bitfields.atc); dbgdev_address_watch_diq()
450 packets_vec[0].reg_data[0] = cntl.u32All; dbgdev_address_watch_diq()
478 cntl.bitfields.valid = 1; dbgdev_address_watch_diq()
480 cntl.bitfields.valid = 0; dbgdev_address_watch_diq()
492 packets_vec[3].reg_data[0] = cntl.u32All; dbgdev_address_watch_diq()
239 dbgdev_address_watch_set_registers( const struct dbg_address_watch_info *adw_info, union TCP_WATCH_ADDR_H_BITS *addrHi, union TCP_WATCH_ADDR_L_BITS *addrLo, union TCP_WATCH_CNTL_BITS *cntl, unsigned int index, unsigned int vmid) dbgdev_address_watch_set_registers() argument
/linux-4.4.14/include/linux/amba/
H A Dclcd.h102 u32 cntl; member in struct:clcd_panel
115 u32 cntl; member in struct:clcd_regs
204 if (fb->panel->cntl & CNTL_LCDDUAL) clcdfb_decode()
217 if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */ clcdfb_decode()
221 else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */ clcdfb_decode()
230 val = fb->panel->cntl; clcdfb_decode()
278 regs->cntl = val; clcdfb_decode()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c505 union TCP_WATCH_CNTL_BITS cntl; kgd_address_watch_disable() local
508 cntl.u32All = 0; kgd_address_watch_disable()
510 cntl.bitfields.valid = 0; kgd_address_watch_disable()
511 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; kgd_address_watch_disable()
512 cntl.bitfields.atc = 1; kgd_address_watch_disable()
517 ADDRESS_WATCH_REG_CNTL], cntl.u32All); kgd_address_watch_disable()
529 union TCP_WATCH_CNTL_BITS cntl; kgd_address_watch_execute() local
531 cntl.u32All = cntl_val; kgd_address_watch_execute()
534 cntl.bitfields.valid = 0; kgd_address_watch_execute()
536 ADDRESS_WATCH_REG_CNTL], cntl.u32All); kgd_address_watch_execute()
545 cntl.bitfields.valid = 1; kgd_address_watch_execute()
548 ADDRESS_WATCH_REG_CNTL], cntl.u32All); kgd_address_watch_execute()
H A Dkv_dpm.h85 u32 cntl; member in struct:kv_lcac_config_reg
H A Dkv_dpm.c408 WREG32_SMC(local_cac_reg->cntl, data);
/linux-4.4.14/drivers/spi/
H A Dspi-bcm2835aux.c102 u32 cntl[2]; member in struct:bcm2835aux_spi
232 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] | __bcm2835aux_spi_transfer_one_irq()
247 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); bcm2835aux_spi_transfer_one_irq()
248 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); bcm2835aux_spi_transfer_one_irq()
271 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]); bcm2835aux_spi_transfer_one_poll()
272 bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL0, bs->cntl[0]); bcm2835aux_spi_transfer_one_poll()
333 bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE | bcm2835aux_spi_transfer_one()
336 bs->cntl[1] = BCM2835_AUX_SPI_CNTL1_MSBF_IN; bcm2835aux_spi_transfer_one()
351 bs->cntl[0] |= speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT; bcm2835aux_spi_transfer_one()
357 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPOL; bcm2835aux_spi_transfer_one()
359 bs->cntl[0] |= BCM2835_AUX_SPI_CNTL0_CPHA_OUT | bcm2835aux_spi_transfer_one()
/linux-4.4.14/arch/arm/mach-nspire/
H A Dclcd.c37 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
59 .cntl = CNTL_LCDMONO8,
/linux-4.4.14/drivers/i2c/busses/
H A Di2c-ibm_iic.c88 " cntl = 0x%02x, mdcntl = 0x%02x\n" dump_iic_regs()
92 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), dump_iic_regs()
165 out_8(&iic->cntl, 0); iic_dev_init()
385 out_8(&iic->cntl, CNTL_HMT); iic_abort_xfer()
468 u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT; iic_xfer_bytes() local
470 cntl |= CNTL_RW; iic_xfer_bytes()
475 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT); iic_xfer_bytes()
477 if (!(cntl & CNTL_RW)) iic_xfer_bytes()
489 out_8(&iic->cntl, cmd); iic_xfer_bytes()
508 if (cntl & CNTL_RW) iic_xfer_bytes()
528 out_8(&iic->cntl, CNTL_AMD); iic_address()
533 out_8(&iic->cntl, 0); iic_address()
H A Di2c-ibm_iic.h32 u8 cntl; member in struct:iic_regs
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_kfd.c701 union TCP_WATCH_CNTL_BITS cntl; kgd_address_watch_disable() local
704 cntl.u32All = 0; kgd_address_watch_disable()
706 cntl.bitfields.valid = 0; kgd_address_watch_disable()
707 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; kgd_address_watch_disable()
708 cntl.bitfields.atc = 1; kgd_address_watch_disable()
715 cntl.u32All); kgd_address_watch_disable()
726 union TCP_WATCH_CNTL_BITS cntl; kgd_address_watch_execute() local
728 cntl.u32All = cntl_val; kgd_address_watch_execute()
731 cntl.bitfields.valid = 0; kgd_address_watch_execute()
735 cntl.u32All); kgd_address_watch_execute()
748 cntl.bitfields.valid = 1; kgd_address_watch_execute()
753 cntl.u32All); kgd_address_watch_execute()
H A Dkv_dpm.h59 u32 cntl; member in struct:kv_lcac_config_reg
H A Dradeon_dp_mst.c171 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe); radeon_dp_mst_set_vcp_size()
H A Dkv_dpm.c275 WREG32_SMC(local_cac_reg->cntl, data);
/linux-4.4.14/arch/m68k/include/asm/
H A Dmac_oss.h67 __u8 rom_ctrl; /* [0x204-0x204] ROM cntl reg (for poweroff) */
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
H A Dmtd-xip.h22 u32 cntl; /* CNTL_TIMER, R/W */ member in struct:__anon235
/linux-4.4.14/drivers/net/ethernet/micrel/
H A Dks8851_mll.c1057 u16 cntl; ks_start_rx() local
1060 cntl = ks_rdreg16(ks, KS_RXCR1); ks_start_rx()
1061 cntl |= RXCR1_RXE ; ks_start_rx()
1062 ks_wrreg16(ks, KS_RXCR1, cntl); ks_start_rx()
1072 u16 cntl; ks_stop_rx() local
1075 cntl = ks_rdreg16(ks, KS_RXCR1); ks_stop_rx()
1076 cntl &= ~RXCR1_RXE ; ks_stop_rx()
1077 ks_wrreg16(ks, KS_RXCR1, cntl); ks_stop_rx()
1147 u16 cntl; ks_set_promis() local
1150 cntl = ks_rdreg16(ks, KS_RXCR1); ks_set_promis()
1152 cntl &= ~RXCR1_FILTER_MASK; ks_set_promis()
1155 cntl |= RXCR1_RXAE | RXCR1_RXINVF; ks_set_promis()
1158 cntl |= RXCR1_RXPAFMA; ks_set_promis()
1160 ks_wrreg16(ks, KS_RXCR1, cntl); ks_set_promis()
1169 u16 cntl; ks_set_mcast() local
1173 cntl = ks_rdreg16(ks, KS_RXCR1); ks_set_mcast()
1174 cntl &= ~RXCR1_FILTER_MASK; ks_set_mcast()
1177 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA); ks_set_mcast()
1183 cntl |= RXCR1_RXPAFMA; ks_set_mcast()
1185 ks_wrreg16(ks, KS_RXCR1, cntl); ks_set_mcast()
/linux-4.4.14/arch/powerpc/platforms/cell/spufs/
H A Dcontext.c137 if (ctx->cntl) spu_unmap_mappings()
138 unmap_mapping_range(ctx->cntl, 0, SPUFS_CNTL_MAP_SIZE, 1); spu_unmap_mappings()
H A Dspufs.h85 struct address_space *cntl; /* 'control' area mappings. */ member in struct:spu_context
H A Dfile.c436 ctx->cntl = inode->i_mapping; spufs_cntl_open()
452 ctx->cntl = NULL; spufs_cntl_release()
2637 { "cntl", &spufs_cntl_fops, 0666, },
2679 { "cntl", &spufs_cntl_fops, 0666, },
/linux-4.4.14/drivers/net/wireless/ath/ath6kl/
H A Dcommon.h65 u8 cntl; member in struct:ath6kl_llc_snap_hdr
H A Dwmi.c197 llc_hdr->cntl = 0x03; ath6kl_wmi_dix_2_dot3()
/linux-4.4.14/arch/arm/mach-integrator/
H A Dimpd1.c95 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
123 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
151 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
183 .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
/linux-4.4.14/arch/arm/mach-footbridge/
H A Ddc21285.c190 unsigned int cntl; dc21285_serr_irq() local
196 cntl = *CSR_SA110_CNTL & 0xffffdf07; dc21285_serr_irq()
197 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR; dc21285_serr_irq()
/linux-4.4.14/arch/arm/mach-netx/
H A Dnxdb500.c56 .cntl = CNTL_LCDTFT | CNTL_BGR,
H A Dnxeb500hmi.c56 .cntl = CNTL_LCDTFT | CNTL_BGR,
/linux-4.4.14/drivers/media/platform/soc_camera/
H A Dmx2_camera.c753 u32 cntl; mx2_stop_streaming() local
757 cntl = readl(pcdev->base_emma + PRP_CNTL); mx2_stop_streaming()
759 writel(cntl & ~PRP_CNTL_CH1EN, mx2_stop_streaming()
762 writel(cntl & ~PRP_CNTL_CH2EN, mx2_stop_streaming()
1412 u32 cntl = readl(pcdev->base_emma + PRP_CNTL); mx27_camera_emma_irq() local
1413 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN), mx27_camera_emma_irq()
1415 writel(cntl, pcdev->base_emma + PRP_CNTL); mx27_camera_emma_irq()
/linux-4.4.14/drivers/staging/dgap/
H A Ddgap.h735 unsigned char startc; /* flow cntl start char */
736 unsigned char stopc; /* flow cntl stop char */
740 #define F2200_GETA (('e'<<8) | 104) /* Get 2x36 flow cntl flags */
741 #define F2200_SETAW (('e'<<8) | 105) /* Set 2x36 flow cntl flags */
742 #define F2200_MASK 0x03 /* 2200 flow cntl bit mask */
743 #define FCNTL_2200 0x01 /* 2x36 terminal flow cntl */
744 #define PCNTL_2200 0x02 /* 2x36 printer flow cntl */
/linux-4.4.14/arch/powerpc/include/asm/
H A Ducc_slow.h53 #define R_C 0x08000000 /* the last byte in this buffer is a cntl
/linux-4.4.14/arch/arm/mach-lpc32xx/
H A Dphy3250.c79 .cntl = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
/linux-4.4.14/arch/arm/mach-ixp4xx/
H A Ddsmg600-setup.c165 /* enable the pwr cntl and drive it high */ dsmg600_power_off()
H A Dnas100d-setup.c187 /* enable the pwr cntl gpio and assert power off */ nas100d_power_off()
H A Dnslu2-setup.c200 /* enable the pwr cntl gpio and assert power off */ nslu2_power_off()
/linux-4.4.14/drivers/scsi/
H A Dadvansys.c262 uchar cntl; member in struct:asc_scsiq_1
306 uchar cntl; member in struct:asc_q_done_info
358 uchar cntl; member in struct:asc_sg_list_q
608 ushort cntl; member in struct:asceep_config
1752 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ member in struct:adv_scsi_req_q
2589 printk(" cntl 0x%x, data_addr 0x%lx\n", asc_prt_adv_scsi_req_q()
2590 q->cntl, (ulong)le32_to_cpu(q->data_addr)); asc_prt_adv_scsi_req_q()
2913 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); asc_prt_asc_board_eeprom()
6212 scsiq->cntl = 0; AdvISR()
6714 scsiq->cntl = (uchar)_val; _AscCopyLramScsiDoneQ()
6896 if ((scsiq->cntl & QC_SG_HEAD) != 0) { AscIsrQDone()
6964 cntl & (QC_DATA_IN | QC_DATA_OUT)) AscIsrQDone()
6990 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { AscIsrQDone()
7008 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { AscIsrQDone()
7590 asc_scsi_q->q1.cntl |= QC_SG_HEAD; asc_build_req()
7767 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0; adv_build_req()
7984 scsiq->q1.cntl |= QC_MSG_OUT; AscPutReadyQueue()
7997 (uchar *)&scsiq->q1.cntl, AscPutReadyQueue()
8036 scsiq->q1.cntl |= QC_SG_HEAD; AscPutReadySgListQueue()
8041 scsi_sg_q.cntl = QCSG_SG_XFER_LIST; AscPutReadySgListQueue()
8059 scsi_sg_q.cntl |= QCSG_SG_XFER_END; AscPutReadySgListQueue()
8091 scsiq->q1.cntl &= ~QC_SG_HEAD; AscPutReadySgListQueue()
8202 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); AscExeScsiQueue()
8210 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { AscExeScsiQueue()
8222 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE); AscExeScsiQueue()
8230 if (scsiq->q1.cntl & QC_SG_HEAD) { AscExeScsiQueue()
8266 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { AscExeScsiQueue()
8310 || ((scsiq->q1.cntl & QC_URGENT) != 0)) { AscExeScsiQueue()
8354 ((scsiq->q1.cntl & QC_URGENT) != 0)) { AscExeScsiQueue()
8912 /* Don't swap word field at the end - cntl field. */ AscGetEEPConfig()
9032 /* Don't swap word field at the end - cntl field. */ AscSetEEPConfigOnce()
9073 /* Don't swap word field at the end - cntl field. */ AscSetEEPConfigOnce()
9177 eep_config->cntl = 0xBFFF; AscInitFromEEP()
9199 asc_dvc->dvc_cntl = eep_config->cntl; AscInitFromEEP()
11063 ep->cntl = asc_dvc_varp->dvc_cntl; advansys_board_found()
/linux-4.4.14/arch/arm/mach-versatile/
H A Dcore.c563 regs->cntl &= ~CNTL_BGR; versatile_clcd_decode()
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_display.c9933 uint32_t cntl = 0, size = 0; i845_update_cursor() local
9953 cntl |= CURSOR_ENABLE | i845_update_cursor()
9964 intel_crtc->cursor_cntl != cntl)) { i845_update_cursor()
9983 if (intel_crtc->cursor_cntl != cntl) { i845_update_cursor()
9984 I915_WRITE(CURCNTR(PIPE_A), cntl); i845_update_cursor() local
9986 intel_crtc->cursor_cntl = cntl; i845_update_cursor()
9996 uint32_t cntl = 0; i9xx_update_cursor() local
9999 cntl = MCURSOR_GAMMA_ENABLE; i9xx_update_cursor()
10002 cntl |= CURSOR_MODE_64_ARGB_AX; i9xx_update_cursor()
10005 cntl |= CURSOR_MODE_128_ARGB_AX; i9xx_update_cursor()
10008 cntl |= CURSOR_MODE_256_ARGB_AX; i9xx_update_cursor()
10014 cntl |= pipe << 28; /* Connect to correct pipe */ i9xx_update_cursor()
10017 cntl |= CURSOR_PIPE_CSC_ENABLE; i9xx_update_cursor()
10021 cntl |= CURSOR_ROTATE_180; i9xx_update_cursor()
10023 if (intel_crtc->cursor_cntl != cntl) { i9xx_update_cursor()
10024 I915_WRITE(CURCNTR(pipe), cntl); i9xx_update_cursor() local
10026 intel_crtc->cursor_cntl = cntl; i9xx_update_cursor()
/linux-4.4.14/drivers/power/
H A Daxp288_fuel_gauge.c1016 dev_err(&info->pdev->dev, "gauge cntl set fail:%d\n", ret); fuel_gauge_init_config_regs()
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A Dar9003_phy.c2215 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", ar9003_hw_bb_watchdog_dbg_info()
/linux-4.4.14/drivers/scsi/lpfc/
H A Dlpfc_hbadisc.c715 "WRK Enable ring: cntl:x%x hacopy:x%x", lpfc_work_done()
723 "WRK Ring ok: cntl:x%x hacopy:x%x", lpfc_work_done()

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