Searched refs:PIPECONF (Results 1 – 5 of 5) sorted by relevance
1139 int reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()1361 u32 val = I915_READ(PIPECONF(cpu_transcoder)); in assert_pipe()1990 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()2038 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()2147 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()2187 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()3803 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()3873 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()3901 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()4199 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()[all …]
504 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
681 dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & in intel_dsi_get_hw_state()
4468 #define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) macro
5581 u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder); in intel_dp_set_drrs_state()