1139 		int reg = PIPECONF(cpu_transcoder);  in intel_wait_for_pipe_off()
1361 		u32 val = I915_READ(PIPECONF(cpu_transcoder));  in assert_pipe()
1990 	pipeconf_val = I915_READ(PIPECONF(pipe));  in ironlake_enable_pch_transcoder()
2038 	pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));  in lpt_enable_pch_transcoder()
2147 	reg = PIPECONF(cpu_transcoder);  in intel_enable_pipe()
2187 	reg = PIPECONF(cpu_transcoder);  in intel_disable_pipe()
3803 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ironlake_fdi_pll_enable()
3873 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ironlake_fdi_disable()
3901 	temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;  in ironlake_fdi_disable()
4199 		u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;  in ironlake_pch_enable()
7792 	if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {  in intel_get_pipe_timings()
7840 		pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;  in i9xx_set_pipeconf()
7889 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
7890 	POSTING_READ(PIPECONF(intel_crtc->pipe));  in i9xx_set_pipeconf()
8143 	tmp = I915_READ(PIPECONF(crtc->pipe));  in i9xx_get_pipe_config()
8649 	I915_WRITE(PIPECONF(pipe), val);  in ironlake_set_pipeconf()
8650 	POSTING_READ(PIPECONF(pipe));  in ironlake_set_pipeconf()
8736 	I915_WRITE(PIPECONF(cpu_transcoder), val);  in haswell_set_pipeconf()
8737 	POSTING_READ(PIPECONF(cpu_transcoder));  in haswell_set_pipeconf()
9274 	tmp = I915_READ(PIPECONF(crtc->pipe));  in ironlake_get_pipe_config()
9888 	tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));  in haswell_get_pipe_config()
15060 	reg = PIPECONF(crtc->config->cpu_transcoder);  in intel_sanitize_crtc()
15741 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));  in intel_display_capture_error_state()