Searched refs:HIWORD_UPDATE (Results 1 - 9 of 9) sorted by relevance

/linux-4.4.14/drivers/clk/rockchip/
H A Dclk-pll.c196 writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0), rockchip_rk3066_pll_set_params()
200 writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK, rockchip_rk3066_pll_set_params()
202 HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK, rockchip_rk3066_pll_set_params()
206 writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK, rockchip_rk3066_pll_set_params()
209 writel_relaxed(HIWORD_UPDATE(rate->nb - 1, RK3066_PLLCON2_NB_MASK, rockchip_rk3066_pll_set_params()
214 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0), rockchip_rk3066_pll_set_params()
264 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), rockchip_rk3066_pll_enable()
274 writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN, rockchip_rk3066_pll_disable()
H A Dclk-cpu.c159 writel(HIWORD_UPDATE(alt_div, reg_data->div_core_mask, rockchip_cpuclk_pre_rate_change()
161 HIWORD_UPDATE(1, 1, reg_data->mux_core_shift), rockchip_cpuclk_pre_rate_change()
165 writel(HIWORD_UPDATE(1, 1, reg_data->mux_core_shift), rockchip_cpuclk_pre_rate_change()
199 writel(HIWORD_UPDATE(0, reg_data->div_core_mask, rockchip_cpuclk_post_rate_change()
201 HIWORD_UPDATE(0, 1, reg_data->mux_core_shift), rockchip_cpuclk_post_rate_change()
H A Dclk-mmc-phase.c126 writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift), mmc_clock->reg); rockchip_mmc_set_phase()
169 writel(HIWORD_UPDATE(ROCKCHIP_MMC_INIT_STATE_RESET, rockchip_clk_register_mmc()
H A Dclk-inverter.c58 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), rockchip_inv_set_phase()
H A Dclk-rk3188.c119 .val = HIWORD_UPDATE(_core_peri, RK3066_DIV_CORE_PERIPH_MASK, \
125 .val = HIWORD_UPDATE(_aclk_core, RK3066_DIV_ACLK_CORE_MASK, \
127 HIWORD_UPDATE(_aclk_hclk, RK3066_DIV_ACLK_HCLK_MASK, \
129 HIWORD_UPDATE(_aclk_pclk, RK3066_DIV_ACLK_PCLK_MASK, \
131 HIWORD_UPDATE(_ahb2apb, RK3066_DIV_AHB2APB_MASK, \
167 .val = HIWORD_UPDATE(_aclk_core, RK3188_DIV_ACLK_CORE_MASK,\
H A Dclk-rk3288.c121 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
123 HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
129 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK, \
131 HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK, \
133 HIWORD_UPDATE(_pclk_dbg_pre, \
H A Dclk-rk3368.c188 .val = HIWORD_UPDATE(_aclkm, RK3368_DIV_ACLKM_MASK, \
194 .val = HIWORD_UPDATE(_atclk, RK3368_DIV_ATCLK_MASK, \
196 HIWORD_UPDATE(_pdbg, RK3368_DIV_PCLK_DBG_MASK, \
H A Dclk.h30 #define HIWORD_UPDATE(val, mask, shift) \ macro
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c69 #define HIWORD_UPDATE(val, mask, shift) \ macro
100 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
101 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
212 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
213 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)

Completed in 437 milliseconds