Searched refs:ARC_REG_TLBPD0 (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/arch/arc/include/asm/
H A Dtlb-mmu1.h60 ; lr r1,[ARC_REG_TLBPD0] /* Data VPN+ASID - already in r1 from TLB_RELOAD*/
64 lr r1,[ARC_REG_TLBPD0] /* save TLBPD0 containing data TLB*/
65 sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
68 sr r1,[ARC_REG_TLBPD0] /* restore TLBPD0 */
88 sr r0,[ARC_REG_TLBPD0] /* write instruction address to TLBPD0 */
91 sr r3,[ARC_REG_TLBPD0] /* restore TLBPD0 */
H A Dmmu.h25 #define ARC_REG_TLBPD0 0x405 macro
33 #define ARC_REG_TLBPD0 0x460 macro
/linux-4.4.14/arch/arc/mm/
H A Dtlb.c116 write_aux_reg(ARC_REG_TLBPD0, 0); __tlb_entry_erase()
126 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); tlb_entry_lkup()
228 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT); tlb_entry_erase()
234 write_aux_reg(ARC_REG_TLBPD0, pd0); tlb_entry_insert()
264 write_aux_reg(ARC_REG_TLBPD0, 0); local_flush_tlb_all()
276 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ); local_flush_tlb_all()
901 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); do_tlb_overlap_fault()
H A Dtlbex.S274 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
277 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0

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