Searched refs:RD_REG_DWORD (Results 1 – 14 of 14) sorted by relevance
154 stat = RD_REG_DWORD(®->host_status); in qla27xx_dump_mpi_ram()168 RD_REG_DWORD(®->hccr); in qla27xx_dump_mpi_ram()174 RD_REG_DWORD(®->hccr); in qla27xx_dump_mpi_ram()232 stat = RD_REG_DWORD(®->host_status); in qla24xx_dump_ram()245 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()251 RD_REG_DWORD(®->hccr); in qla24xx_dump_ram()302 *buf++ = htonl(RD_REG_DWORD(dmp_reg++)); in qla24xx_read_window()314 if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) in qla24xx_pause_risc()333 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_soft_reset()338 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_soft_reset()[all …]
371 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)381 RD_REG_DWORD((ha)->cregbase + off)387 RD_REG_DWORD((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)400 RD_REG_DWORD((ha)->cregbase + off)
682 RD_REG_DWORD(®->rsp_q_out); in qlafx00_config_rings()913 pseudo_aen = RD_REG_DWORD(®->pseudoaen); in qlafx00_init_fw_ready()915 aenmbx7 = RD_REG_DWORD(®->initval7); in qlafx00_init_fw_ready()926 aenmbx = RD_REG_DWORD(®->aenmailbox0); in qlafx00_init_fw_ready()945 aenmbx7 = RD_REG_DWORD(®->aenmailbox7); in qlafx00_init_fw_ready()948 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1); in qlafx00_init_fw_ready()949 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3); in qlafx00_init_fw_ready()950 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5); in qlafx00_init_fw_ready()951 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6); in qlafx00_init_fw_ready()983 aenmbx7 = RD_REG_DWORD(®->initval7); in qlafx00_init_fw_ready()[all …]
464 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 && in qla24xx_read_flash_dword()476 data = RD_REG_DWORD(®->flash_data); in qla24xx_read_flash_dword()504 RD_REG_DWORD(®->flash_data); /* PCI Posting. */ in qla24xx_write_flash_dword()508 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) && in qla24xx_write_flash_dword()1143 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()1144 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()1182 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()1183 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_protect_flash()1410 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()1411 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()[all …]
178 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2300_intr_handler()2615 RD_REG_DWORD(®->iobase_addr); in qla2xxx_check_risc_status()2617 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()2630 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && in qla2xxx_check_risc_status()2642 if (RD_REG_DWORD(®->iobase_c8) & BIT_3) in qla2xxx_check_risc_status()2648 RD_REG_DWORD(®->iobase_window); in qla2xxx_check_risc_status()2691 stat = RD_REG_DWORD(®->host_status); in qla24xx_intr_handler()2698 hccr = RD_REG_DWORD(®->hccr); in qla24xx_intr_handler()2781 stat = RD_REG_DWORD(®->host_status); in qla24xx_msix_rsp_q()2856 stat = RD_REG_DWORD(®->host_status); in qla24xx_msix_default()[all …]
367 win_read = RD_REG_DWORD((void __iomem *) in qla82xx_pci_set_crbwindow_2M()508 data = RD_REG_DWORD((void __iomem *)off); in qla82xx_rd_32()929 RD_REG_DWORD((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); in qla82xx_md_rw_32()937 rval = RD_REG_DWORD((void __iomem *) in qla82xx_md_rw_32()2059 if (RD_REG_DWORD(®->host_int)) { in qla82xx_intr_handler()2060 stat = RD_REG_DWORD(®->host_status); in qla82xx_intr_handler()2125 host_int = RD_REG_DWORD(®->host_int); in qla82xx_msix_default()2129 stat = RD_REG_DWORD(®->host_status); in qla82xx_msix_default()2186 host_int = RD_REG_DWORD(®->host_int); in qla82xx_msix_rsp_q()2221 host_int = RD_REG_DWORD(®->host_int); in qla82xx_poll()[all …]
890 ha->pci_attr = RD_REG_DWORD(®->ctrl_status); in qla24xx_pci_config()1145 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) in qla24xx_reset_risc()1151 if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) in qla24xx_reset_risc()1156 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()1157 RD_REG_DWORD(®->ctrl_status), in qla24xx_reset_risc()1158 (RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)); in qla24xx_reset_risc()1182 RD_REG_DWORD(®->hccr), in qla24xx_reset_risc()1183 RD_REG_DWORD(®->mailbox0)); in qla24xx_reset_risc()1186 d2 = RD_REG_DWORD(®->ctrl_status); in qla24xx_reset_risc()1189 if ((RD_REG_DWORD(®->ctrl_status) & in qla24xx_reset_risc()[all …]
1862 cnt = RD_REG_DWORD(®->isp25mq.req_q_out); in qla2x00_alloc_iocbs()1864 cnt = RD_REG_DWORD(®->isp82.req_q_out); in qla2x00_alloc_iocbs()1866 cnt = RD_REG_DWORD(®->isp24.req_q_out); in qla2x00_alloc_iocbs()1868 cnt = RD_REG_DWORD(®->ispfx00.req_q_out); in qla2x00_alloc_iocbs()2548 while (RD_REG_DWORD((void __iomem *)ha->nxdb_rd_ptr) != dbval) { in qla82xx_start_scsi()
157 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()187 if (RD_REG_DWORD(®->isp82.hint) & in qla2x00_mailbox_command()272 ictrl = RD_REG_DWORD(®->isp24.ictrl); in qla2x00_mailbox_command()384 RD_REG_DWORD(®->isp24.host_status), in qla2x00_mailbox_command()386 RD_REG_DWORD(®->isp24.ictrl), in qla2x00_mailbox_command()387 RD_REG_DWORD(®->isp24.istatus)); in qla2x00_mailbox_command()4645 stat = RD_REG_DWORD(®->host_status); in qla81xx_write_mpi_register()4656 RD_REG_DWORD(®->hccr); in qla81xx_write_mpi_register()
1492 RD_REG_DWORD(®->ictrl); in qla24xx_enable_intrs()1507 RD_REG_DWORD(®->ictrl); in qla24xx_disable_intrs()5444 stat = RD_REG_DWORD(®->hccr); in qla2xxx_pci_mmio_enabled()5448 stat = RD_REG_DWORD(®->u.isp2300.host_status); in qla2xxx_pci_mmio_enabled()5452 stat = RD_REG_DWORD(®24->host_status); in qla2xxx_pci_mmio_enabled()5675 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & in qla83xx_disable_laser()
167 value = RD_REG_DWORD((__iomem void *)window); in qla27xx_read32()
3941 if (RD_REG_DWORD(®->host_int)) { in qla8044_intr_handler()3942 stat = RD_REG_DWORD(®->host_status); in qla8044_intr_handler()
1691 cnt = (uint16_t)RD_REG_DWORD(vha->req->req_q_out); in qlt_check_reserve_free_req()1692 cnt_in = (uint16_t)RD_REG_DWORD(vha->req->req_q_in); in qlt_check_reserve_free_req()6188 RD_REG_DWORD(ISP_ATIO_Q_OUT(vha)); in qlt_24xx_config_rings()
111 #define RD_REG_DWORD(addr) readl(addr) macro