890 	ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);  in qla24xx_pci_config()
1145 		if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
1151 	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
1156 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1157 	    RD_REG_DWORD(&reg->ctrl_status),  in qla24xx_reset_risc()
1158 	    (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
1182 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1183 	    RD_REG_DWORD(&reg->mailbox0));  in qla24xx_reset_risc()
1186 	d2 = RD_REG_DWORD(&reg->ctrl_status);  in qla24xx_reset_risc()
1189 		if ((RD_REG_DWORD(&reg->ctrl_status) &  in qla24xx_reset_risc()
1195 	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
1200 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1201 	    RD_REG_DWORD(&reg->ctrl_status));  in qla24xx_reset_risc()
1221 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
1224 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
1227 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_risc()
1243 	    RD_REG_DWORD(&reg->hccr),  in qla24xx_reset_risc()
1264 	*data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);  in qla25xx_read_risc_sema_reg()
2168 	RD_REG_DWORD(&ioreg->hccr);  in qla24xx_config_rings()
5032 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_adapter()
5034 	RD_REG_DWORD(&reg->hccr);  in qla24xx_reset_adapter()