| H A D | dmascc.c | 234 static void write_scc(struct scc_priv *priv, int reg, int val);
295 write_scc(&info->priv[0], R9, FHWRES); dmascc_exit()
464 /* Initialize what is necessary for write_scc and write_scc_data */ setup_adapter()
494 write_scc(priv, R9, FHWRES | MIE | NV); setup_adapter()
497 write_scc(priv, R15, SHDLCE); setup_adapter()
512 write_scc(priv, R15, 0); setup_adapter()
525 write_scc(priv, R15, CTSIE); setup_adapter()
526 write_scc(priv, R0, RES_EXT_INT); setup_adapter()
527 write_scc(priv, R1, EXT_INT_ENAB); setup_adapter()
543 write_scc(priv, R1, 0); setup_adapter()
544 write_scc(priv, R15, 0); setup_adapter()
545 write_scc(priv, R0, RES_EXT_INT); setup_adapter()
608 write_scc(&info->priv[0], R9, FHWRES); setup_adapter()
621 static void write_scc(struct scc_priv *priv, int reg, int val) write_scc() function
755 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); scc_open()
757 write_scc(priv, R4, SDLC | X1CLK); scc_open()
759 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); scc_open()
761 write_scc(priv, R3, Rx8); scc_open()
763 write_scc(priv, R5, Tx8); scc_open()
765 write_scc(priv, R6, 0); scc_open()
767 write_scc(priv, R7, FLAG); scc_open()
771 write_scc(priv, R15, SHDLCE); scc_open()
773 write_scc(priv, R7, AUTOEOM); scc_open()
774 write_scc(priv, R15, 0); scc_open()
778 write_scc(priv, R15, SHDLCE); scc_open()
800 write_scc(priv, R7, AUTOEOM | TXFIFOE); scc_open()
802 write_scc(priv, R7, AUTOEOM); scc_open()
804 write_scc(priv, R7, AUTOEOM | RXFIFOH); scc_open()
806 write_scc(priv, R15, 0); scc_open()
810 write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ)); scc_open()
815 write_scc(priv, R12, priv->param.brg_tc & 0xFF); scc_open()
816 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF); scc_open()
819 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL); scc_open()
821 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL); scc_open()
824 write_scc(priv, R14, DTRREQ | BRSRC); scc_open()
834 write_scc(priv, R11, priv->param.clocks); scc_open()
853 write_scc(priv, R15, DCDIE); scc_open()
877 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); scc_close()
952 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8); scc_send_packet()
953 write_scc(priv, R15, 0); scc_send_packet()
989 write_scc(priv, R15, TxUIE); tx_on()
996 write_scc(priv, R1, tx_on()
1007 write_scc(priv, R15, TxUIE); tx_on()
1008 write_scc(priv, R1, tx_on()
1014 write_scc(priv, R0, RES_EOM_L); tx_on()
1042 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx | rx_on()
1048 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT | rx_on()
1051 write_scc(priv, R0, ERR_RES); rx_on()
1052 write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB); rx_on()
1059 write_scc(priv, R3, Rx8); rx_off()
1064 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); rx_off()
1080 write_scc(priv, R15, r15 | CTSIE); start_timer()
1112 write_scc(&info->priv[0], R0, RES_H_IUS); z8530_isr()
1167 write_scc(priv, R0, ERR_RES); rx_isr()
1199 write_scc(priv, R0, ERR_RES); special_condition()
1298 write_scc(priv, R0, RES_Tx_P); tx_isr()
1309 write_scc(priv, R0, RES_EOM_L); tx_isr()
1322 write_scc(priv, R0, RES_EXT_INT); es_isr()
1344 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN); es_isr()
1350 write_scc(priv, R0, RES_EXT_INT); es_isr()
1351 write_scc(priv, R0, RES_EXT_INT); es_isr()
1363 write_scc(priv, R15, 0); es_isr()
1381 write_scc(priv, R15, 0); es_isr()
1389 write_scc(priv, R15, 0); es_isr()
1411 write_scc(priv, R5, TxCRC_ENAB | Tx8); tm_isr()
1414 write_scc(priv, R15, 0); tm_isr()
1418 write_scc(priv, R15, DCDIE); tm_isr()
1433 write_scc(priv, R5, tm_isr()
1435 write_scc(priv, R15, 0); tm_isr()
1440 write_scc(priv, R15, DCDIE); tm_isr()
1445 write_scc(priv, R15, DCDIE); tm_isr()
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