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Searched refs:write_csr (Results 1 – 15 of 15) sorted by relevance

/linux-4.4.14/drivers/staging/rdma/hfi1/
Deprom.c109 write_csr(dd, ASIC_GPIO_OUT, in write_enable()
112 write_csr(dd, ASIC_GPIO_OE, in write_enable()
122 write_csr(dd, ASIC_GPIO_OUT, in write_disable()
125 write_csr(dd, ASIC_GPIO_OE, in write_disable()
140 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_SR1); in wait_for_not_busy()
157 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); in wait_for_not_busy()
168 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_MANUF_DEV_ID); in read_device_id()
181 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE); in erase_chip()
182 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_CHIP_ERASE); in erase_chip()
210 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_WRITE_ENABLE); in erase_32kb_range()
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Dchip.c1261 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) in write_csr() function
1283 write_csr(dd, csr, value); in read_write_csr()
2317 write_csr(dd, SEND_EGRESS_ERR_INFO, info); in handle_send_egress_err_info()
2603 write_csr(dd, in handle_qsfp_int()
2625 write_csr(dd, in handle_qsfp_int()
2682 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_host_lcb_access()
2693 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_8051_lcb_access()
2816 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, in hreq_response()
2836 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); in handle_8051_request()
2874 write_csr(dd, SEND_CM_GLOBAL_CREDIT, in write_global_credit()
[all …]
Dfirmware.c254 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in __read_8051_data()
288 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); in read_8051_data()
297 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); in read_8051_data()
320 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); in write_8051()
325 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in write_8051()
339 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); in write_8051()
356 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); in write_8051()
357 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); in write_8051()
655 write_csr(dd, what + (8*i), *ptr); in write_rsa_data()
662 write_csr(dd, what + (8*i), value); in write_rsa_data()
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Dpcie.c842 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), in write_gasket_interrupt()
862 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); in arm_gasket_logic()
943 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in do_pcie_gen3_transition()
1131 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in do_pcie_gen3_transition()
1179 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); in do_pcie_gen3_transition()
1201 write_csr(dd, CCE_DC_CTRL, 0); in do_pcie_gen3_transition()
1251 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in do_pcie_gen3_transition()
Dchip.h553 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
571 write_csr(dd, offset0 + (0x100 * ctxt), value); in write_kctxt_csr()
606 write_csr(dd, offset0 + (0x1000 * ctxt), value); in write_uctxt_csr()
Dpio.c70 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK); in __cm_reset()
131 write_csr(dd, SEND_CTRL, reg); in pio_send_control()
1150 write_csr(dd, SEND_PIO_ERR_CLEAR, in pio_reset_all()
1155 write_csr(dd, SEND_PIO_INIT_CTXT, in pio_reset_all()
1227 write_csr(dd, SEND_PIO_INIT_CTXT, pio); in sc_enable()
Dhfi.h1826 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); in setextled()
1828 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); in setextled()
Ddiag.c709 write_csr(dd, DCC_CFG_PORT_CONFIG1, in hfi1_snoop_open()
765 write_csr(dd, DCC_CFG_PORT_CONFIG1, dd->hfi1_snoop.dcc_cfg); in hfi1_snoop_release()
Dmad.c1476 write_csr(dd, SEND_SC2VLT0, *val++); in set_sc2vlt_tables()
1477 write_csr(dd, SEND_SC2VLT1, *val++); in set_sc2vlt_tables()
1478 write_csr(dd, SEND_SC2VLT2, *val++); in set_sc2vlt_tables()
1479 write_csr(dd, SEND_SC2VLT3, *val++); in set_sc2vlt_tables()
3128 write_csr(dd, RCV_ERR_INFO, in pma_set_opa_errorinfo()
Dinit.c406 write_csr(dd, SEND_STATIC_RATE_CONTROL, src); in set_link_ipg()
Dsdma.c3084 write_csr(sde->dd, in _sdma_engine_progress_schedule()
/linux-4.4.14/drivers/net/ethernet/amd/
Dpcnet32.c247 void (*write_csr) (unsigned long, int, u16); member
384 .write_csr = pcnet32_wio_write_csr,
439 .write_csr = pcnet32_dwio_write_csr,
465 lp->a->write_csr(ioaddr, CSR3, val); in pcnet32_netif_start()
797 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ in pcnet32_set_ringparam()
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ in pcnet32_loopback_test()
899 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ in pcnet32_loopback_test()
907 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ in pcnet32_loopback_test()
958 lp->a->write_csr(ioaddr, CSR15, x | 0x0044); in pcnet32_loopback_test()
961 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ in pcnet32_loopback_test()
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/linux-4.4.14/drivers/firewire/
Dcore.h91 void (*write_csr)(struct fw_card *card, int csr_offset, u32 value); member
Dcore-transaction.c1120 card->driver->write_csr(card, reg, be32_to_cpu(*data)); in handle_registers()
1127 card->driver->write_csr(card, CSR_STATE_CLEAR, in handle_registers()
Dohci.c3519 .write_csr = ohci_write_csr,