Searched refs:wcreg (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/sound/pci/
H A Drme32.c199 u32 wcreg; /* cached write control register value */ member in struct:rme32
237 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
401 writel(rme32->wcreg | RME32_WCR_PD, snd_rme32_reset_dac()
403 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_reset_dac()
410 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + snd_rme32_playback_getrate()
411 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); snd_rme32_playback_getrate()
425 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; snd_rme32_playback_getrate()
494 ds = rme32->wcreg & RME32_WCR_DS_BM; snd_rme32_playback_setrate()
497 rme32->wcreg &= ~RME32_WCR_DS_BM; snd_rme32_playback_setrate()
498 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & snd_rme32_playback_setrate()
502 rme32->wcreg &= ~RME32_WCR_DS_BM; snd_rme32_playback_setrate()
503 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & snd_rme32_playback_setrate()
507 rme32->wcreg &= ~RME32_WCR_DS_BM; snd_rme32_playback_setrate()
508 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | snd_rme32_playback_setrate()
514 rme32->wcreg |= RME32_WCR_DS_BM; snd_rme32_playback_setrate()
515 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & snd_rme32_playback_setrate()
521 rme32->wcreg |= RME32_WCR_DS_BM; snd_rme32_playback_setrate()
522 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & snd_rme32_playback_setrate()
528 rme32->wcreg |= RME32_WCR_DS_BM; snd_rme32_playback_setrate()
529 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | snd_rme32_playback_setrate()
535 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || snd_rme32_playback_setrate()
536 (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) snd_rme32_playback_setrate()
541 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_playback_setrate()
551 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & snd_rme32_setclockmode()
556 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & snd_rme32_setclockmode()
561 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | snd_rme32_setclockmode()
566 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | snd_rme32_setclockmode()
572 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_setclockmode()
578 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + snd_rme32_getclockmode()
579 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); snd_rme32_getclockmode()
586 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & snd_rme32_setinputtype()
590 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & snd_rme32_setinputtype()
594 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | snd_rme32_setinputtype()
598 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | snd_rme32_setinputtype()
604 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_setinputtype()
610 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + snd_rme32_getinputtype()
611 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); snd_rme32_getinputtype()
626 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; snd_rme32_setframelog()
629 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; snd_rme32_setframelog()
638 rme32->wcreg &= ~RME32_WCR_MODE24; snd_rme32_setformat()
641 rme32->wcreg |= RME32_WCR_MODE24; snd_rme32_setformat()
646 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_setformat()
695 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { snd_rme32_playback_hw_params()
696 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); snd_rme32_playback_hw_params()
697 rme32->wcreg |= rme32->wcreg_spdif_stream; snd_rme32_playback_hw_params()
698 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_playback_hw_params()
726 rme32->wcreg |= RME32_WCR_AUTOSYNC; snd_rme32_capture_hw_params()
727 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_capture_hw_params()
749 rme32->wcreg &= ~RME32_WCR_AUTOSYNC; snd_rme32_capture_hw_params()
750 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_capture_hw_params()
781 rme32->wcreg |= RME32_WCR_START; snd_rme32_pcm_start()
782 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_pcm_start()
795 rme32->wcreg &= ~RME32_WCR_START; snd_rme32_pcm_stop()
796 if (rme32->wcreg & RME32_WCR_SEL) snd_rme32_pcm_stop()
797 rme32->wcreg |= RME32_WCR_MUTE; snd_rme32_pcm_stop()
798 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_pcm_stop()
856 rme32->wcreg &= ~RME32_WCR_ADAT; snd_rme32_playback_spdif_open()
857 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_playback_spdif_open()
938 rme32->wcreg |= RME32_WCR_ADAT; snd_rme32_playback_adat_open()
939 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_playback_adat_open()
1001 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; snd_rme32_playback_close()
1035 if (rme32->wcreg & RME32_WCR_SEL) snd_rme32_playback_prepare()
1036 rme32->wcreg &= ~RME32_WCR_MUTE; snd_rme32_playback_prepare()
1037 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_playback_prepare()
1438 rme32->wcreg = RME32_WCR_SEL | /* normal playback */ snd_rme32_create()
1441 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_create()
1483 if (rme32->wcreg & RME32_WCR_MODE24) { snd_rme32_proc_read()
1488 if (rme32->wcreg & RME32_WCR_MONO) { snd_rme32_proc_read()
1522 if (rme32->wcreg & RME32_WCR_SEL) { snd_rme32_proc_read()
1527 if (rme32->wcreg & RME32_WCR_MUTE) { snd_rme32_proc_read()
1535 ((!(rme32->wcreg & RME32_WCR_FREQ_0)) snd_rme32_proc_read()
1536 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { snd_rme32_proc_read()
1545 if (rme32->wcreg & RME32_WCR_PRO) { snd_rme32_proc_read()
1550 if (rme32->wcreg & RME32_WCR_EMP) { snd_rme32_proc_read()
1579 rme32->wcreg & RME32_WCR_SEL ? 0 : 1; snd_rme32_get_loopback_control()
1593 val = (rme32->wcreg & ~RME32_WCR_SEL) | val; snd_rme32_put_loopback_control()
1594 change = val != rme32->wcreg; snd_rme32_put_loopback_control()
1599 rme32->wcreg = val; snd_rme32_put_loopback_control()
1809 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); snd_rme32_control_spdif_stream_put()
1810 rme32->wcreg |= val; snd_rme32_control_spdif_stream_put()
1811 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); snd_rme32_control_spdif_stream_put()
H A Drme96.c233 u32 wcreg; /* cached write control register value */ member in struct:rme96
275 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
276 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
540 writel(rme96->wcreg | RME96_WCR_PD, snd_rme96_reset_dac()
542 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_reset_dac()
548 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + snd_rme96_getmontracks()
549 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); snd_rme96_getmontracks()
557 rme96->wcreg |= RME96_WCR_MONITOR_0; snd_rme96_setmontracks()
559 rme96->wcreg &= ~RME96_WCR_MONITOR_0; snd_rme96_setmontracks()
562 rme96->wcreg |= RME96_WCR_MONITOR_1; snd_rme96_setmontracks()
564 rme96->wcreg &= ~RME96_WCR_MONITOR_1; snd_rme96_setmontracks()
566 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_setmontracks()
573 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + snd_rme96_getattenuation()
574 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); snd_rme96_getattenuation()
583 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & snd_rme96_setattenuation()
587 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & snd_rme96_setattenuation()
591 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | snd_rme96_setattenuation()
595 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | snd_rme96_setattenuation()
601 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_setattenuation()
673 if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_playback_getrate()
680 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + snd_rme96_playback_getrate()
681 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); snd_rme96_playback_getrate()
695 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; snd_rme96_playback_getrate()
704 ds = rme96->wcreg & RME96_WCR_DS; snd_rme96_playback_setrate()
707 rme96->wcreg &= ~RME96_WCR_DS; snd_rme96_playback_setrate()
708 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & snd_rme96_playback_setrate()
712 rme96->wcreg &= ~RME96_WCR_DS; snd_rme96_playback_setrate()
713 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & snd_rme96_playback_setrate()
717 rme96->wcreg &= ~RME96_WCR_DS; snd_rme96_playback_setrate()
718 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | snd_rme96_playback_setrate()
722 rme96->wcreg |= RME96_WCR_DS; snd_rme96_playback_setrate()
723 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & snd_rme96_playback_setrate()
727 rme96->wcreg |= RME96_WCR_DS; snd_rme96_playback_setrate()
728 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & snd_rme96_playback_setrate()
732 rme96->wcreg |= RME96_WCR_DS; snd_rme96_playback_setrate()
733 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | snd_rme96_playback_setrate()
739 if ((!ds && rme96->wcreg & RME96_WCR_DS) || snd_rme96_playback_setrate()
740 (ds && !(rme96->wcreg & RME96_WCR_DS))) snd_rme96_playback_setrate()
746 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_playback_setrate()
800 rme96->wcreg &= ~RME96_WCR_MASTER; snd_rme96_setclockmode()
805 rme96->wcreg |= RME96_WCR_MASTER; snd_rme96_setclockmode()
810 rme96->wcreg |= RME96_WCR_MASTER; snd_rme96_setclockmode()
816 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_setclockmode()
827 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : snd_rme96_getclockmode()
839 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & snd_rme96_setinputtype()
843 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & snd_rme96_setinputtype()
847 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | snd_rme96_setinputtype()
859 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | snd_rme96_setinputtype()
888 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_setinputtype()
898 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + snd_rme96_getinputtype()
899 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); snd_rme96_getinputtype()
916 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; snd_rme96_setframelog()
919 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; snd_rme96_setframelog()
929 rme96->wcreg &= ~RME96_WCR_MODE24; snd_rme96_playback_setformat()
932 rme96->wcreg |= RME96_WCR_MODE24; snd_rme96_playback_setformat()
937 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_playback_setformat()
946 rme96->wcreg &= ~RME96_WCR_MODE24_2; snd_rme96_capture_setformat()
949 rme96->wcreg |= RME96_WCR_MODE24_2; snd_rme96_capture_setformat()
954 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_capture_setformat()
964 rme96->wcreg &= ~RME96_WCR_ISEL; snd_rme96_set_period_properties()
967 rme96->wcreg |= RME96_WCR_ISEL; snd_rme96_set_period_properties()
973 rme96->wcreg &= ~RME96_WCR_IDIS; snd_rme96_set_period_properties()
974 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_set_period_properties()
992 if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_playback_hw_params()
1024 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { snd_rme96_playback_hw_params()
1025 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); snd_rme96_playback_hw_params()
1026 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_playback_hw_params()
1113 rme96->wcreg |= RME96_WCR_START; snd_rme96_trigger()
1115 rme96->wcreg &= ~RME96_WCR_START; snd_rme96_trigger()
1117 rme96->wcreg |= RME96_WCR_START_2; snd_rme96_trigger()
1119 rme96->wcreg &= ~RME96_WCR_START_2; snd_rme96_trigger()
1120 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_trigger()
1192 rme96->wcreg &= ~RME96_WCR_ADAT; snd_rme96_playback_spdif_open()
1193 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_playback_spdif_open()
1198 if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_playback_spdif_open()
1261 rme96->wcreg |= RME96_WCR_ADAT; snd_rme96_playback_adat_open()
1262 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_playback_adat_open()
1267 if (!(rme96->wcreg & RME96_WCR_MASTER) && snd_rme96_playback_adat_open()
1327 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; snd_rme96_playback_close()
1676 rme96->wcreg = snd_rme96_create()
1684 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_create()
1734 if (rme96->wcreg & RME96_WCR_IDIS) { snd_rme96_proc_read()
1737 } else if (rme96->wcreg & RME96_WCR_ISEL) { snd_rme96_proc_read()
1771 if (rme96->wcreg & RME96_WCR_MODE24_2) { snd_rme96_proc_read()
1778 if (rme96->wcreg & RME96_WCR_SEL) { snd_rme96_proc_read()
1785 if (rme96->wcreg & RME96_WCR_MODE24) { snd_rme96_proc_read()
1792 } else if (rme96->wcreg & RME96_WCR_MASTER) { snd_rme96_proc_read()
1801 if (rme96->wcreg & RME96_WCR_PRO) { snd_rme96_proc_read()
1806 if (rme96->wcreg & RME96_WCR_EMP) { snd_rme96_proc_read()
1811 if (rme96->wcreg & RME96_WCR_DOLBY) { snd_rme96_proc_read()
1871 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; snd_rme96_get_loopback_control()
1884 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; snd_rme96_put_loopback_control()
1885 change = val != rme96->wcreg; snd_rme96_put_loopback_control()
1886 rme96->wcreg = val; snd_rme96_put_loopback_control()
2184 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); snd_rme96_control_spdif_stream_put()
2185 rme96->wcreg |= val; snd_rme96_control_spdif_stream_put()
2186 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); snd_rme96_control_spdif_stream_put()

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