233 	u32 wcreg;    /* cached write control register value */  member
275 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
276 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
540 	writel(rme96->wcreg | RME96_WCR_PD,  in snd_rme96_reset_dac()
542 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_reset_dac()
548 	return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +  in snd_rme96_getmontracks()
549 		(((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);  in snd_rme96_getmontracks()
557 		rme96->wcreg |= RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
559 		rme96->wcreg &= ~RME96_WCR_MONITOR_0;  in snd_rme96_setmontracks()
562 		rme96->wcreg |= RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
564 		rme96->wcreg &= ~RME96_WCR_MONITOR_1;  in snd_rme96_setmontracks()
566 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setmontracks()
573 	return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +  in snd_rme96_getattenuation()
574 		(((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);  in snd_rme96_getattenuation()
583 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
587 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &  in snd_rme96_setattenuation()
591 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
595 		rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |  in snd_rme96_setattenuation()
601 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setattenuation()
673 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_getrate()
680 	rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +  in snd_rme96_playback_getrate()
681 		(((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);  in snd_rme96_playback_getrate()
695 	return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;  in snd_rme96_playback_getrate()
704 	ds = rme96->wcreg & RME96_WCR_DS;  in snd_rme96_playback_setrate()
707 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
708 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
712 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
713 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
717 		rme96->wcreg &= ~RME96_WCR_DS;  in snd_rme96_playback_setrate()
718 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
722 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
723 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &  in snd_rme96_playback_setrate()
727 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
728 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &  in snd_rme96_playback_setrate()
732 		rme96->wcreg |= RME96_WCR_DS;  in snd_rme96_playback_setrate()
733 		rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |  in snd_rme96_playback_setrate()
739 	if ((!ds && rme96->wcreg & RME96_WCR_DS) ||  in snd_rme96_playback_setrate()
740 	    (ds && !(rme96->wcreg & RME96_WCR_DS)))  in snd_rme96_playback_setrate()
746 		writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setrate()
800 		rme96->wcreg &= ~RME96_WCR_MASTER;  in snd_rme96_setclockmode()
805 		rme96->wcreg |= RME96_WCR_MASTER;  in snd_rme96_setclockmode()
810 		rme96->wcreg |= RME96_WCR_MASTER;   in snd_rme96_setclockmode()
816 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setclockmode()
827 	return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :  in snd_rme96_getclockmode()
839 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
843 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &  in snd_rme96_setinputtype()
847 		rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
859 		rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |  in snd_rme96_setinputtype()
888 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_setinputtype()
898 	return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +  in snd_rme96_getinputtype()
899 		(((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);  in snd_rme96_getinputtype()
916 		frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;  in snd_rme96_setframelog()
919 		frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;  in snd_rme96_setframelog()
929 		rme96->wcreg &= ~RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
932 		rme96->wcreg |= RME96_WCR_MODE24;  in snd_rme96_playback_setformat()
937 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_setformat()
946 		rme96->wcreg &= ~RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
949 		rme96->wcreg |= RME96_WCR_MODE24_2;  in snd_rme96_capture_setformat()
954 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_capture_setformat()
964 		rme96->wcreg &= ~RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
967 		rme96->wcreg |= RME96_WCR_ISEL;  in snd_rme96_set_period_properties()
973 	rme96->wcreg &= ~RME96_WCR_IDIS;  in snd_rme96_set_period_properties()
974 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_set_period_properties()
992 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_hw_params()
1024 	if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {  in snd_rme96_playback_hw_params()
1025 		rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_playback_hw_params()
1026 		writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_hw_params()
1113 		rme96->wcreg |= RME96_WCR_START;  in snd_rme96_trigger()
1115 		rme96->wcreg &= ~RME96_WCR_START;  in snd_rme96_trigger()
1117 		rme96->wcreg |= RME96_WCR_START_2;  in snd_rme96_trigger()
1119 		rme96->wcreg &= ~RME96_WCR_START_2;  in snd_rme96_trigger()
1120 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_trigger()
1192 	rme96->wcreg &= ~RME96_WCR_ADAT;  in snd_rme96_playback_spdif_open()
1193 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_spdif_open()
1198 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_spdif_open()
1261 	rme96->wcreg |= RME96_WCR_ADAT;  in snd_rme96_playback_adat_open()
1262 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_playback_adat_open()
1267 	if (!(rme96->wcreg & RME96_WCR_MASTER) &&  in snd_rme96_playback_adat_open()
1327 	spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;  in snd_rme96_playback_close()
1676 	rme96->wcreg =  in snd_rme96_create()
1684 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_create()
1734 	if (rme96->wcreg & RME96_WCR_IDIS) {  in snd_rme96_proc_read()
1737 	} else if (rme96->wcreg & RME96_WCR_ISEL) {  in snd_rme96_proc_read()
1771 	if (rme96->wcreg & RME96_WCR_MODE24_2) {  in snd_rme96_proc_read()
1778 	if (rme96->wcreg & RME96_WCR_SEL) {  in snd_rme96_proc_read()
1785 	if (rme96->wcreg & RME96_WCR_MODE24) {  in snd_rme96_proc_read()
1792 	} else if (rme96->wcreg & RME96_WCR_MASTER) {  in snd_rme96_proc_read()
1801 	if (rme96->wcreg & RME96_WCR_PRO) {  in snd_rme96_proc_read()
1806 	if (rme96->wcreg & RME96_WCR_EMP) {  in snd_rme96_proc_read()
1811 	if (rme96->wcreg & RME96_WCR_DOLBY) {  in snd_rme96_proc_read()
1871 	ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;  in snd_rme96_get_loopback_control()
1884 	val = (rme96->wcreg & ~RME96_WCR_SEL) | val;  in snd_rme96_put_loopback_control()
1885 	change = val != rme96->wcreg;  in snd_rme96_put_loopback_control()
1886 	rme96->wcreg = val;  in snd_rme96_put_loopback_control()
2184 	rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);  in snd_rme96_control_spdif_stream_put()
2185 	rme96->wcreg |= val;  in snd_rme96_control_spdif_stream_put()
2186 	writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);  in snd_rme96_control_spdif_stream_put()