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Searched refs:vlv_dpio_write (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_hdmi.c1582 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_hdmi_pre_enable()
1585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); in vlv_hdmi_pre_enable()
1586 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); in vlv_hdmi_pre_enable()
1587 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); in vlv_hdmi_pre_enable()
1588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); in vlv_hdmi_pre_enable()
1589 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); in vlv_hdmi_pre_enable()
1590 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_hdmi_pre_enable()
1591 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_enable()
1592 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_enable()
1595 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_hdmi_pre_enable()
[all …]
Dintel_dp.c2414 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
2422 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
2431 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
2440 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
2767 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_pre_enable_dp()
2768 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_pre_enable_dp()
2769 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_pre_enable_dp()
2790 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_dp_pre_pll_enable()
2793 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_dp_pre_pll_enable()
2800 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_dp_pre_pll_enable()
[all …]
Dintel_sideband.c205 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) in vlv_dpio_write() function
Dintel_display.c1655 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); in chv_enable_pll()
1831 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); in chv_disable_pll()
7213 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
7218 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
7222 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
7227 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
7350 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); in vlv_prepare_pll()
7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); in vlv_prepare_pll()
7358 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
7372 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
[all …]
Dintel_runtime_pm.c1127 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); in chv_dpio_cmn_power_well_enable()
1132 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); in chv_dpio_cmn_power_well_enable()
1141 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); in chv_dpio_cmn_power_well_enable()
Di915_drv.h3405 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);