Lines Matching refs:vlv_dpio_write
2414 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
2422 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
2431 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
2440 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
2767 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_pre_enable_dp()
2768 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_pre_enable_dp()
2769 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_pre_enable_dp()
2790 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_dp_pre_pll_enable()
2793 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_dp_pre_pll_enable()
2800 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_dp_pre_pll_enable()
2801 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_dp_pre_pll_enable()
2802 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_dp_pre_pll_enable()
2824 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_pre_enable_dp()
2829 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_pre_enable_dp()
2839 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_pre_enable_dp()
2857 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_pre_enable_dp()
2862 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_pre_enable_dp()
2865 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), in chv_pre_enable_dp()
2873 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), in chv_pre_enable_dp()
2933 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_dp_pre_pll_enable()
2941 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_dp_pre_pll_enable()
2951 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_dp_pre_pll_enable()
2960 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_dp_pre_pll_enable()
2973 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_dp_pre_pll_enable()
2990 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_dp_post_pll_disable()
2994 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_dp_post_pll_disable()
3234 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); in vlv_signal_levels()
3235 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); in vlv_signal_levels()
3236 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), in vlv_signal_levels()
3238 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); in vlv_signal_levels()
3239 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_signal_levels()
3240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); in vlv_signal_levels()
3241 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); in vlv_signal_levels()
3342 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_signal_levels()
3349 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_signal_levels()
3355 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_signal_levels()
3361 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_signal_levels()
3369 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_signal_levels()
3387 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_signal_levels()
3402 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_signal_levels()
3408 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_signal_levels()
3413 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_signal_levels()