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Searched refs:vlv_dpio_read (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_hdmi.c1575 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1650 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
1658 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
1666 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
1675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
1715 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1723 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1733 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1741 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1754 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
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Dintel_dp.c2409 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
2417 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
2425 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
2434 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_pre_enable_dp()
2822 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_pre_enable_dp()
2827 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_pre_enable_dp()
2855 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_pre_enable_dp()
2860 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_pre_enable_dp()
2927 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_dp_pre_pll_enable()
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Dintel_sideband.c188 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) in vlv_dpio_read() function
Dintel_runtime_pm.c1124 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable()
1130 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable()
1139 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable()
1208 val = vlv_dpio_read(dev_priv, pipe, reg); in assert_chv_phy_powergate()
Dintel_display.c1653 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1829 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
7210 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
7215 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
7220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
7224 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
7353 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
7405 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
7479 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
7487 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
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Di915_drv.h3404 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);