1653 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));  in chv_enable_pll()
1829 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));  in chv_disable_pll()
7210 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));  in vlv_pllb_recal_opamp()
7215 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);  in vlv_pllb_recal_opamp()
7220 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));  in vlv_pllb_recal_opamp()
7224 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);  in vlv_pllb_recal_opamp()
7353 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));  in vlv_prepare_pll()
7405 	coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));  in vlv_prepare_pll()
7479 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_prepare_pll()
7487 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));  in chv_prepare_pll()
7520 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));  in chv_prepare_pll()
7527 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |  in chv_prepare_pll()
8018 	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));  in vlv_crtc_clock_get()
8111 	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));  in chv_crtc_clock_get()
8112 	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));  in chv_crtc_clock_get()
8113 	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));  in chv_crtc_clock_get()
8114 	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));  in chv_crtc_clock_get()
8115 	pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_crtc_clock_get()