Searched refs:vlv (Results 1 - 13 of 13) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_pm.c289 dev_priv->wm.vlv.cxsr = enable; intel_set_memory_cxsr()
1312 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { vlv_update_wm()
1319 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) vlv_update_wm()
1323 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) vlv_update_wm()
1326 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) vlv_update_wm()
1340 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) vlv_update_wm()
1344 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) vlv_update_wm()
1348 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) vlv_update_wm()
1351 dev_priv->wm.vlv = wm; vlv_update_wm()
3998 struct vlv_wm_values *wm = &dev_priv->wm.vlv; vlv_wm_get_hw_state()
6539 * WaVSThreadDispatchOverride:ivb,vlv gen7_setup_fixed_func_scheduler()
6814 /* WaDisableEarlyCull:vlv */ valleyview_init_clock_gating()
6818 /* WaDisableBackToBackFlipFix:vlv */ valleyview_init_clock_gating()
6823 /* WaPsdDispatchEnable:vlv */ valleyview_init_clock_gating()
6824 /* WaDisablePSDDualDispatchEnable:vlv */ valleyview_init_clock_gating()
6829 /* WaDisable_RenderCache_OperationalFlush:vlv */ valleyview_init_clock_gating()
6832 /* WaForceL3Serialization:vlv */ valleyview_init_clock_gating()
6836 /* WaDisableDopClockGating:vlv */ valleyview_init_clock_gating()
6840 /* This is required by WaCatErrorRejectionIssue:vlv */ valleyview_init_clock_gating()
6849 * This implements the WaDisableRCZUnitClockGating:vlv workaround. valleyview_init_clock_gating()
6854 /* WaDisableL3Bank2xClockGate:vlv valleyview_init_clock_gating()
6879 * WaIncreaseL3CreditsForVLVB0:vlv valleyview_init_clock_gating()
6885 * WaDisableVLVClockGating_VBIIssue:vlv valleyview_init_clock_gating()
H A Di915_reg.h371 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
1450 * [0-15] @ 0x100000 gen6,vlv,chv
1942 #define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
2940 /* vlv source selection */
4361 #define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
4552 #define DSPARB2 (VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
4571 /* pnv/gen4/g4x/vlv/chv */
4579 #define DSPFW_PLANEB_MASK_VLV (0xff<<8) /* vlv/chv */
4582 #define DSPFW_PLANEA_MASK_VLV (0xff<<0) /* vlv/chv */
4591 #define DSPFW_SPRITEB_MASK_VLV (0xff<<16) /* vlv/chv */
4598 #define DSPFW_SPRITEA_MASK_VLV (0xff<<0) /* vlv/chv */
4609 /* vlv/chv */
4658 /* vlv/chv high order bits */
4661 #define DSPFW_SR_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
4682 #define DSPFW_SR_WM1_HI_MASK (3<<24) /* 2 bits for chv, 1 for vlv */
6534 /* vlv has 2 sets of panel control regs. */
H A Di915_gem_context.c550 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ mi_set_context()
573 * WaMiSetContext_Hang:snb,ivb,vlv
H A Dintel_uncore.c193 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ fw_domains_get_with_thread_status()
1232 ASSIGN_READ_MMIO_VFUNCS(vlv); intel_uncore_init()
H A Dintel_ringbuffer.c1175 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv init_render_ring()
1186 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ init_render_ring()
H A Di915_gem_execbuffer.c1530 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure i915_gem_do_execbuffer()
H A Dintel_hdmi.c1284 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi intel_hdmi_compute_config()
H A Di915_drv.h1636 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1936 struct vlv_wm_values vlv; member in union:drm_i915_private::__anon4248::__anon4249
H A Dintel_lrc.c1529 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv gen8_init_render_ring()
H A Di915_debugfs.c4352 * - latencies are in us on gen9/vlv/chv wm_latency_show()
H A Di915_irq.c4392 /* WaGsvRC0ResidencyMethod:vlv */ intel_irq_init()
H A Dintel_display.c4792 dev_priv->wm.vlv.cxsr = false; intel_pre_disable_primary()
6684 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. intel_crtc_compute_config()
11499 /* vlv: DISPLAY_FLIP fails to change tiling */ intel_crtc_page_flip()
14854 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ i915_disable_vga()
H A Dintel_dp.c6037 /* eDP only on port B and/or C on vlv/chv */ intel_dp_init_connector()

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