Searched refs:ulv (Results 1 - 13 of 13) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dsi_dpm.c4647 struct si_ulv_param *ulv = &si_pi->ulv; si_populate_ulv_state() local
4651 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, si_populate_ulv_state()
4660 if (ulv->one_pcie_lane_in_ulv) si_populate_ulv_state()
4676 struct si_ulv_param *ulv = &si_pi->ulv; si_program_ulv_memory_timing_parameters() local
4680 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, si_program_ulv_memory_timing_parameters()
4686 ulv->volt_change_delay); si_program_ulv_memory_timing_parameters()
4711 const struct si_ulv_param *ulv = &si_pi->ulv; si_init_smc_table() local
4771 if (ulv->supported && ulv->pl.vddc) { si_init_smc_table()
4780 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); si_init_smc_table()
4781 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); si_init_smc_table()
5150 struct si_ulv_param *ulv = &si_pi->ulv; si_disable_ulv() local
5152 if (ulv->supported) si_disable_ulv()
5163 const struct si_ulv_param *ulv = &si_pi->ulv; si_is_state_ulv_compatible() local
5167 if (state->performance_levels[0].mclk != ulv->pl.mclk) si_is_state_ulv_compatible()
5175 if (ulv->pl.vddc < si_is_state_ulv_compatible()
5191 const struct si_ulv_param *ulv = &si_pi->ulv; si_set_power_state_conditionally_enable_ulv() local
5193 if (ulv->supported) { si_set_power_state_conditionally_enable_ulv()
5309 struct si_ulv_param *ulv = &si_pi->ulv; si_upload_ulv_state() local
5312 if (ulv->supported && ulv->pl.vddc) { si_upload_ulv_state()
5668 struct si_ulv_param *ulv = &si_pi->ulv; si_populate_mc_reg_table() local
5685 if (ulv->supported && ulv->pl.vddc != 0) si_populate_mc_reg_table()
5686 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, si_populate_mc_reg_table()
6784 si_pi->ulv.supported = false; si_parse_pplib_clock_info()
6785 si_pi->ulv.pl = *pl; si_parse_pplib_clock_info()
6786 si_pi->ulv.one_pcie_lane_in_ulv = false; si_parse_pplib_clock_info()
6787 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; si_parse_pplib_clock_info()
6788 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; si_parse_pplib_clock_info()
6789 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; si_parse_pplib_clock_info()
H A Dsi_dpm.h160 struct si_ulv_param ulv; member in struct:si_power_info
H A Dcypress_dpm.h87 struct evergreen_ulv_param ulv; member in struct:evergreen_power_info
H A Dci_dpm.h231 struct ci_ulv_parm ulv; member in struct:ci_power_info
H A Dbtc_dpm.c1390 if (eg_pi->ulv.supported) { btc_disable_ulv()
1402 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; btc_populate_ulv_state()
1676 if (eg_pi->ulv.supported) { btc_init_smc_table()
1679 eg_pi->ulv.supported = false; btc_init_smc_table()
1787 if (eg_pi->ulv.supported) btc_set_boot_state_timing()
1796 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; btc_is_state_ulv_compatible()
1814 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; btc_set_ulv_dram_timing()
1843 if (eg_pi->ulv.supported) { btc_set_power_state_conditionally_enable_ulv()
2567 eg_pi->ulv.supported = false; btc_dpm_init()
H A Dci_dpm.c3078 struct ci_ulv_parm *ulv = &pi->ulv; ci_enable_ulv() local
3080 if (ulv->supported) { ci_enable_ulv()
3102 pi->ulv.supported = false; ci_populate_ulv_level()
3528 struct ci_ulv_parm *ulv = &pi->ulv; ci_init_smc_table() local
3551 if (ulv->supported) { ci_init_smc_table()
3555 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); ci_init_smc_table()
5467 pi->ulv.supported = true; ci_parse_pplib_clock_info()
5468 pi->ulv.pl = *pl; ci_parse_pplib_clock_info()
5469 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; ci_parse_pplib_clock_info()
H A Drv770_dpm.c2237 eg_pi->ulv.supported = true; rv7xx_parse_pplib_clock_info()
2238 eg_pi->ulv.pl = pl; rv7xx_parse_pplib_clock_info()
H A Dr600_dpm.c122 printk("ulv "); r600_dpm_print_class_info()
H A Dcypress_dpm.c2036 eg_pi->ulv.supported = false; cypress_dpm_init()
H A Dni_dpm.c3956 eg_pi->ulv.supported = true; ni_parse_pplib_clock_info()
3957 eg_pi->ulv.pl = pl; ni_parse_pplib_clock_info()
4062 eg_pi->ulv.supported = false; ni_dpm_init()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dci_dpm.h232 struct ci_ulv_parm ulv; member in struct:ci_power_info
H A Dci_dpm.c3216 struct ci_ulv_parm *ulv = &pi->ulv; ci_enable_ulv() local
3218 if (ulv->supported) { ci_enable_ulv()
3240 pi->ulv.supported = false; ci_populate_ulv_level()
3664 struct ci_ulv_parm *ulv = &pi->ulv; ci_init_smc_table() local
3687 if (ulv->supported) { ci_init_smc_table()
3691 WREG32_SMC(ixCG_ULV_PARAMETER, ulv->cg_ulv_parameter); ci_init_smc_table()
5613 pi->ulv.supported = true; ci_parse_pplib_clock_info()
5614 pi->ulv.pl = *pl; ci_parse_pplib_clock_info()
5615 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; ci_parse_pplib_clock_info()
H A Damdgpu_dpm.c84 printk("ulv "); amdgpu_dpm_print_class_info()

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