4647 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_ulv_state()  local
4651 	ret = si_convert_power_level_to_smc(rdev, &ulv->pl,  in si_populate_ulv_state()
4660 		if (ulv->one_pcie_lane_in_ulv)  in si_populate_ulv_state()
4676 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_program_ulv_memory_timing_parameters()  local
4680 	ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,  in si_program_ulv_memory_timing_parameters()
4686 				   ulv->volt_change_delay);  in si_program_ulv_memory_timing_parameters()
4711 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_init_smc_table()  local
4771 	if (ulv->supported && ulv->pl.vddc) {  in si_init_smc_table()
4780 		WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);  in si_init_smc_table()
4781 		WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);  in si_init_smc_table()
5150 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_disable_ulv()  local
5152 	if (ulv->supported)  in si_disable_ulv()
5163 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_is_state_ulv_compatible()  local
5167 	if (state->performance_levels[0].mclk != ulv->pl.mclk)  in si_is_state_ulv_compatible()
5175 			if (ulv->pl.vddc <  in si_is_state_ulv_compatible()
5191 	const struct si_ulv_param *ulv = &si_pi->ulv;  in si_set_power_state_conditionally_enable_ulv()  local
5193 	if (ulv->supported) {  in si_set_power_state_conditionally_enable_ulv()
5309 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_upload_ulv_state()  local
5312 	if (ulv->supported && ulv->pl.vddc) {  in si_upload_ulv_state()
5668 	struct si_ulv_param *ulv = &si_pi->ulv;  in si_populate_mc_reg_table()  local
5685 	if (ulv->supported && ulv->pl.vddc != 0)  in si_populate_mc_reg_table()
5686 		si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,  in si_populate_mc_reg_table()
6784 		si_pi->ulv.supported = false;  in si_parse_pplib_clock_info()
6785 		si_pi->ulv.pl = *pl;  in si_parse_pplib_clock_info()
6786 		si_pi->ulv.one_pcie_lane_in_ulv = false;  in si_parse_pplib_clock_info()
6787 		si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;  in si_parse_pplib_clock_info()
6788 		si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;  in si_parse_pplib_clock_info()
6789 		si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;  in si_parse_pplib_clock_info()