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Searched refs:ti_clk_ll_ops (Results 1 – 15 of 15) sorted by relevance

/linux-4.4.14/drivers/clk/ti/
Dclkt_dflt.c67 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic()
102 if (!(ti_clk_ll_ops->clk_readl(companion_reg) & in _omap2_module_wait_ready()
108 r = ti_clk_ll_ops->cm_split_idlest_reg(idlest_reg, &prcm_mod, in _omap2_module_wait_ready()
115 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, in _omap2_module_wait_ready()
215 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_dflt_clk_enable()
233 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); in omap2_dflt_clk_enable()
238 ti_clk_ll_ops->clk_writel(v, clk->enable_reg); in omap2_dflt_clk_enable()
239 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
248 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap2_dflt_clk_enable()
277 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); in omap2_dflt_clk_disable()
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Dapll.c58 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
63 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_enable()
66 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in dra7_apll_enable()
71 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); in dra7_apll_enable()
102 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_disable()
105 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in dra7_apll_disable()
116 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in dra7_apll_is_enabled()
233 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_is_enabled()
259 v = ti_clk_ll_ops->clk_readl(ad->control_reg); in omap2_apll_enable()
262 ti_clk_ll_ops->clk_writel(v, ad->control_reg); in omap2_apll_enable()
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Ddpll3xxx.c57 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in _omap3_dpll_write_clken()
60 ti_clk_ll_ops->clk_writel(v, dd->control_reg); in _omap3_dpll_write_clken()
76 while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
154 if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) == in _omap3_noncore_dpll_lock()
319 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap3_noncore_dpll_program()
322 ti_clk_ll_ops->clk_writel(v, dd->control_reg); in omap3_noncore_dpll_program()
326 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); in omap3_noncore_dpll_program()
353 ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); in omap3_noncore_dpll_program()
357 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap3_noncore_dpll_program()
373 ti_clk_ll_ops->clk_writel(v, dd->control_reg); in omap3_noncore_dpll_program()
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Dclkt_iclk.c39 v = ti_clk_ll_ops->clk_readl(r); in omap2_clkt_iclk_allow_idle()
41 ti_clk_ll_ops->clk_writel(v, r); in omap2_clkt_iclk_allow_idle()
53 v = ti_clk_ll_ops->clk_readl(r); in omap2_clkt_iclk_deny_idle()
55 ti_clk_ll_ops->clk_writel(v, r); in omap2_clkt_iclk_deny_idle()
Ddpll44xx.c52 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
55 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
70 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
73 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
131 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap4_dpll_regm4xen_recalc()
Dautoidle.c76 val = ti_clk_ll_ops->clk_readl(clk->reg); in _allow_autoidle()
83 ti_clk_ll_ops->clk_writel(val, clk->reg); in _allow_autoidle()
90 val = ti_clk_ll_ops->clk_readl(clk->reg); in _deny_autoidle()
97 ti_clk_ll_ops->clk_writel(val, clk->reg); in _deny_autoidle()
Dclk.c33 struct ti_clk_ll_ops *ti_clk_ll_ops; variable
79 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) in ti_clk_setup_ll_ops()
81 if (ti_clk_ll_ops) { in ti_clk_setup_ll_ops()
86 ti_clk_ll_ops = ops; in ti_clk_setup_ll_ops()
Dclockdomain.c65 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_clkops_enable_clkdm()
103 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap2_clkops_disable_clkdm()
Dclkt_dpll.c216 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap2_init_dpll_parent()
252 v = ti_clk_ll_ops->clk_readl(dd->control_reg); in omap2_get_dpll_rate()
259 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); in omap2_get_dpll_rate()
Dmux.c44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
86 val = ti_clk_ll_ops->clk_readl(mux->reg); in ti_clk_mux_set_parent()
90 ti_clk_ll_ops->clk_writel(val, mux->reg); in ti_clk_mux_set_parent()
Dgate.c81 orig_v = ti_clk_ll_ops->clk_readl(parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
86 ti_clk_ll_ops->clk_writel(dummy_v, parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
89 ti_clk_ll_ops->clk_writel(orig_v, parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
Dclock.h275 extern struct ti_clk_ll_ops *ti_clk_ll_ops;
Ddivider.c105 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
233 val = ti_clk_ll_ops->clk_readl(divider->reg); in ti_clk_divider_set_rate()
237 ti_clk_ll_ops->clk_writel(val, divider->reg); in ti_clk_divider_set_rate()
/linux-4.4.14/include/linux/clk/
Dti.h226 struct ti_clk_ll_ops { struct
255 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops); argument
/linux-4.4.14/arch/arm/mach-omap2/
Dclock.c57 static struct ti_clk_ll_ops omap_clk_ll_ops = {