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Searched refs:tegra_dc_writel (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/tegra/
Ddc.c99 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
101 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
121 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
122 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
260 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); in tegra_dc_setup_window()
262 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
263 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
266 tegra_dc_writel(dc, value, DC_WIN_POSITION); in tegra_dc_setup_window()
269 tegra_dc_writel(dc, value, DC_WIN_SIZE); in tegra_dc_setup_window()
277 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); in tegra_dc_setup_window()
[all …]
Drgb.c87 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
149 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
155 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); in tegra_rgb_encoder_enable()
160 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); in tegra_rgb_encoder_enable()
164 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_rgb_encoder_enable()
Dhdmi.c828 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_disable()
873 tegra_dc_writel(dc, VSYNC_H_POSITION(1), in tegra_hdmi_encoder_enable()
875 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, in tegra_hdmi_encoder_enable()
881 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_hdmi_encoder_enable()
885 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_hdmi_encoder_enable()
888 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_hdmi_encoder_enable()
1031 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_hdmi_encoder_enable()
Dsor.c1122 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1574 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
1758 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
1934 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
1937 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
1941 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2014 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2034 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2127 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
Ddrm.h158 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, in tegra_dc_writel() function
Ddsi.c818 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_disable()
864 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_dsi_encoder_enable()