Searched refs:speed_cap_mask (Results 1 - 7 of 7) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c334 speed_cap_mask[cfg_idx])); bnx2x_check_lfa()
336 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { bnx2x_check_lfa()
339 params->speed_cap_mask[cfg_idx]); bnx2x_check_lfa()
3448 params->phy[actual_phy_idx].speed_cap_mask = set_phy_vars()
3449 params->speed_cap_mask[link_cfg_idx]; set_phy_vars()
3459 " speed_cap_mask %x\n", set_phy_vars()
3462 params->phy[actual_phy_idx].speed_cap_mask); set_phy_vars()
3766 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || bnx2x_warpcore_enable_AN_KR()
3776 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || bnx2x_warpcore_enable_AN_KR()
3839 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || bnx2x_warpcore_enable_AN_KR()
4492 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) bnx2x_sfp_e3_set_transmitter()
4993 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) bnx2x_set_parallel_detection()
4997 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", bnx2x_set_parallel_detection()
4998 phy->speed_cap_mask, control2); bnx2x_set_parallel_detection()
5005 (phy->speed_cap_mask & bnx2x_set_parallel_detection()
5117 if (phy->speed_cap_mask & bnx2x_set_autoneg()
5120 if (phy->speed_cap_mask & bnx2x_set_autoneg()
5197 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) bnx2x_set_brcm_cl37_advertisement()
5199 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) bnx2x_set_brcm_cl37_advertisement()
5992 (phy->speed_cap_mask >= bnx2x_prepare_xgxs()
5994 (phy->speed_cap_mask < bnx2x_prepare_xgxs()
7465 if (phy->speed_cap_mask & bnx2x_8073_config_init()
7470 if (phy->speed_cap_mask & bnx2x_8073_config_init()
7480 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && bnx2x_8073_config_init()
9122 (phy->speed_cap_mask & bnx2x_8726_config_init()
9124 ((phy->speed_cap_mask & bnx2x_8726_config_init()
9281 ((phy->speed_cap_mask & bnx2x_8727_config_speed()
9283 ((phy->speed_cap_mask & bnx2x_8727_config_speed()
9823 (phy->speed_cap_mask & bnx2x_848xx_cmn_config_init()
9840 if (phy->speed_cap_mask & bnx2x_848xx_cmn_config_init()
9849 if (phy->speed_cap_mask & bnx2x_848xx_cmn_config_init()
9858 if ((phy->speed_cap_mask & bnx2x_848xx_cmn_config_init()
9866 if ((phy->speed_cap_mask & bnx2x_848xx_cmn_config_init()
9917 (phy->speed_cap_mask & bnx2x_848xx_cmn_config_init()
10999 (phy->speed_cap_mask & bnx2x_54618se_config_init()
11019 if (phy->speed_cap_mask & bnx2x_54618se_config_init()
11025 if (phy->speed_cap_mask & bnx2x_54618se_config_init()
11031 if (phy->speed_cap_mask & bnx2x_54618se_config_init()
11037 if (phy->speed_cap_mask & bnx2x_54618se_config_init()
11512 .speed_cap_mask = 0,
11547 .speed_cap_mask = 0,
11583 .speed_cap_mask = 0,
11621 .speed_cap_mask = 0,
11652 .speed_cap_mask = 0,
11683 .speed_cap_mask = 0,
11711 .speed_cap_mask = 0,
11740 .speed_cap_mask = 0,
11772 .speed_cap_mask = 0,
11803 .speed_cap_mask = 0,
11838 .speed_cap_mask = 0,
11875 .speed_cap_mask = 0,
11910 .speed_cap_mask = 0,
11944 .speed_cap_mask = 0,
11978 .speed_cap_mask = 0,
12012 .speed_cap_mask = 0,
12377 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + bnx2x_phy_def_cfg()
12385 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + bnx2x_phy_def_cfg()
12391 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", bnx2x_phy_def_cfg()
12392 phy_index, link_config, phy->speed_cap_mask); bnx2x_phy_def_cfg()
12797 speed_cap_mask[cfg_idx]), bnx2x_cannot_avoid_link_flap()
12798 params->speed_cap_mask[cfg_idx]); bnx2x_cannot_avoid_link_flap()
13811 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) bnx2x_period_func()
H A Dbnx2x_link.h202 u32 speed_cap_mask; member in struct:bnx2x_phy
262 u32 speed_cap_mask[LINK_CONFIG_SIZE]; member in struct:link_params
H A Dbnx2x_ethtool.c490 bp->link_params.speed_cap_mask[cfg_idx] = 0; bnx2x_set_settings()
492 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
496 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
500 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
504 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
508 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
513 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
519 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
523 bp->link_params.speed_cap_mask[cfg_idx] |= bnx2x_set_settings()
H A Dbnx2x_main.c2357 if (lp->speed_cap_mask[cfx_idx] & bnx2x_initial_phy_init()
2361 else if (lp->speed_cap_mask[cfx_idx] & bnx2x_initial_phy_init()
2707 bp->link_params.speed_cap_mask[0] = 0x7f0000; bnx2x__link_status_update()
11188 /* mask what we support according to speed_cap_mask per configuration */ bnx2x_link_settings_supported()
11190 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11194 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11198 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11202 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11206 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11211 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11215 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11219 if (!(bp->link_params.speed_cap_mask[idx] & bnx2x_link_settings_supported()
11276 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11278 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11293 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11295 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11309 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11311 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11327 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11329 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11349 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11351 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11365 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11367 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11388 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n", bnx2x_link_settings_requested()
11390 bp->link_params.speed_cap_mask[idx]); bnx2x_link_settings_requested()
11447 bp->link_params.speed_cap_mask[0] = bnx2x_get_port_hwinfo()
11451 bp->link_params.speed_cap_mask[1] = bnx2x_get_port_hwinfo()
11479 bp->link_params.speed_cap_mask[0], bnx2x_get_port_hwinfo()
H A Dbnx2x_hsi.h2000 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; member in struct:shmem_lfa
/linux-4.4.14/drivers/net/ethernet/qlogic/qed/
H A Dqed_dev.c1158 offsetof(struct nvm_cfg1_port, speed_cap_mask)); qed_hw_get_nvm_info()
H A Dqed_hsi.h3368 u32 adv_speed; /* Default should be the speed_cap_mask */
4711 u32 speed_cap_mask; /* 0x14 */ member in struct:nvm_cfg1_port

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