Searched refs:rtsx_write_register (Results 1 - 10 of 10) sorted by relevance

/linux-4.4.14/drivers/staging/rts5208/
H A Drtsx_chip.c123 retval = rtsx_write_register(chip, CARD_PULL_CTL5, rtsx_pre_handle_sdio_old()
131 retval = rtsx_write_register(chip, FPGA_PULL_CTL, rtsx_pre_handle_sdio_old()
139 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF, rtsx_pre_handle_sdio_old()
147 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01); rtsx_pre_handle_sdio_old()
153 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF, rtsx_pre_handle_sdio_old()
218 retval = rtsx_write_register(chip, 0xFE5A, rtsx_pre_handle_sdio_new()
225 retval = rtsx_write_register(chip, 0xFE70, rtsx_pre_handle_sdio_new()
233 retval = rtsx_write_register(chip, TLPTISTAT, 0xFF, rtsx_pre_handle_sdio_new()
251 retval = rtsx_write_register(chip, rtsx_pre_handle_sdio_new()
268 retval = rtsx_write_register(chip, 0xFE5A, rtsx_pre_handle_sdio_new()
275 retval = rtsx_write_register(chip, 0xFE70, rtsx_pre_handle_sdio_new()
287 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); rtsx_pre_handle_sdio_new()
319 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F); rtsx_reset_aspm()
357 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); rtsx_enable_pcie_intr()
412 retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); rtsx_reset_chip()
419 retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0); rtsx_reset_chip()
428 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0); rtsx_reset_chip()
434 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, rtsx_reset_chip()
442 retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK, rtsx_reset_chip()
448 retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK, rtsx_reset_chip()
454 retval = rtsx_write_register(chip, OCPCTL, 0xFF, rtsx_reset_chip()
462 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, rtsx_reset_chip()
471 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03); rtsx_reset_chip()
479 retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03); rtsx_reset_chip()
486 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0); rtsx_reset_chip()
493 retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF, rtsx_reset_chip()
501 retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF, rtsx_reset_chip()
511 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF, rtsx_reset_chip()
517 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12); rtsx_reset_chip()
532 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10); rtsx_reset_chip()
592 retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, rtsx_reset_chip()
599 retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80); rtsx_reset_chip()
638 retval = rtsx_write_register(chip, SDIO_CTRL, rtsx_reset_chip()
652 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB, rtsx_reset_chip()
663 retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00); rtsx_reset_chip()
671 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03, rtsx_reset_chip()
680 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07); rtsx_reset_chip()
686 retval = rtsx_write_register(chip, PME_FORCE_CTL, rtsx_reset_chip()
694 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04); rtsx_reset_chip()
699 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30); rtsx_reset_chip()
707 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14); rtsx_reset_chip()
723 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, rtsx_reset_chip()
730 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF, rtsx_reset_chip()
788 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); rts5208_init()
861 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03); rts5288_init()
996 retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0); rtsx_init_chip()
1002 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07); rtsx_init_chip()
1141 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, rtsx_monitor_aspm_config()
1244 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data); rtsx_manage_aspm()
1286 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); rtsx_manage_2lun_mode()
1292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); rtsx_manage_2lun_mode()
1309 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); rtsx_manage_1lun_mode()
1312 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); rtsx_manage_1lun_mode()
1315 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); rtsx_manage_1lun_mode()
1338 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1); rtsx_delink_stage1()
1345 rtsx_write_register(chip, CHANGE_LINK_STATE, val, val); rtsx_delink_stage1()
1387 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A); rtsx_delink_stage()
1453 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00); rtsx_undo_delink()
1486 rtsx_write_register(chip, DMACTL, 0x80, 0x80); rtsx_stop_cmd()
1487 rtsx_write_register(chip, RBCTL, 0x80, 0x80); rtsx_stop_cmd()
1492 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data) rtsx_write_register() function
1557 retval = rtsx_write_register(chip, CFGDATA0 + i, rtsx_write_cfg_dw()
1571 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); rtsx_write_cfg_dw()
1576 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, rtsx_write_cfg_dw()
1583 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, rtsx_write_cfg_dw()
1611 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr); rtsx_read_cfg_dw()
1616 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8)); rtsx_read_cfg_dw()
1621 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF, rtsx_read_cfg_dw()
1775 retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val); rtsx_write_phy_register()
1780 retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8)); rtsx_write_phy_register()
1785 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); rtsx_write_phy_register()
1790 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81); rtsx_write_phy_register()
1824 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr); rtsx_read_phy_register()
1829 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80); rtsx_read_phy_register()
1877 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr); rtsx_read_efuse()
1923 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp); rtsx_write_efuse()
1928 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, rtsx_write_efuse()
2017 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); rtsx_check_link_ready()
2064 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT); rtsx_enter_ss()
2076 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01); rtsx_enter_ss()
2086 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0); rtsx_enter_ss()
2227 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); rtsx_do_before_power_down()
2229 rtsx_write_register(chip, 0xFE70, 0x80, 0x80); rtsx_do_before_power_down()
2231 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08); rtsx_do_before_power_down()
2233 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08); rtsx_do_before_power_down()
2240 rtsx_write_register(chip, PETXCFG, 0x08, 0x08); rtsx_do_before_power_down()
2245 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, rtsx_do_before_power_down()
2252 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, rtsx_do_before_power_down()
2257 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2); rtsx_do_before_power_down()
2275 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, rtsx_enable_aspm()
2303 rtsx_write_register(chip, ASPM_FORCE_CTL, rtsx_disable_aspm()
2436 retval = rtsx_write_register(chip, FPDCTL, mask, 0); rtsx_force_power_on()
2467 retval = rtsx_write_register(chip, FPDCTL, mask, val); rtsx_force_power_down()
H A Drtsx_card.c102 rtsx_write_register(chip, SDIO_CTRL, 0xFF, try_to_switch_sdio_ctrl()
104 rtsx_write_register(chip, PWR_GATE_CTRL, try_to_switch_sdio_ctrl()
135 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, dynamic_configure_sdio_aspm()
142 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30); dynamic_configure_sdio_aspm()
166 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); do_reset_sd_card()
191 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); do_reset_sd_card()
220 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); do_reset_xd_card()
244 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); do_reset_xd_card()
268 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); do_reset_ms_card()
292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); do_reset_ms_card()
302 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, release_sdio()
309 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00); release_sdio()
311 rtsx_write_register(chip, 0xFE70, 0x80, 0x00); release_sdio()
314 rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0); release_sdio()
392 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); rtsx_reset_cards()
516 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00); card_cd_debounce()
558 rtsx_write_register(chip, OCPCLR, rtsx_init_cards()
576 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); rtsx_init_cards()
594 rtsx_write_register(chip, HOST_SLEEP_STATE, rtsx_init_cards()
701 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); switch_ssc_clock()
799 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); switch_normal_clock()
805 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, switch_normal_clock()
811 retval = rtsx_write_register(chip, SD_VPCLK1_CTL, switch_normal_clock()
818 retval = rtsx_write_register(chip, CLK_DIV, 0xFF, switch_normal_clock()
824 retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel); switch_normal_clock()
832 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, switch_normal_clock()
838 retval = rtsx_write_register(chip, SD_VPCLK1_CTL, switch_normal_clock()
846 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0); switch_normal_clock()
895 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en); enable_card_clock()
916 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0); disable_card_clock()
976 retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val); card_power_off()
1064 retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value); card_share_mode()
1094 retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod); select_card()
1117 rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg); toggle_gpio()
1123 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), turn_on_led()
1126 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0); turn_on_led()
1132 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0); turn_off_led()
1134 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), turn_off_led()
H A Dspi.c41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, spi_init()
47 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, spi_init()
62 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, spi_set_init_para()
68 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, spi_set_init_para()
87 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, spi_set_init_para()
93 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, spi_set_init_para()
261 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); spi_init_eeprom()
266 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); spi_init_eeprom()
284 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, spi_init_eeprom()
290 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, spi_init_eeprom()
299 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, spi_init_eeprom()
305 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, spi_init_eeprom()
370 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); spi_erase_eeprom_chip()
414 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); spi_erase_eeprom_byte()
465 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); spi_read_eeprom()
510 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); spi_write_eeprom()
H A Dsd.c565 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val); sd_set_sample_push_timing()
629 retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val); sd_set_clock_divider()
756 retval = rtsx_write_register(chip, SD_PAD_CTL, sd_change_bank_voltage()
773 retval = rtsx_write_register(chip, SD_PAD_CTL, sd_change_bank_voltage()
794 retval = rtsx_write_register(chip, SD_BUS_STAT, sd_voltage_switch()
822 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, sd_voltage_switch()
836 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, sd_voltage_switch()
854 rtsx_write_register(chip, SD_BUS_STAT, sd_voltage_switch()
856 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0); sd_voltage_switch()
861 retval = rtsx_write_register(chip, SD_BUS_STAT, sd_voltage_switch()
876 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, sd_reset_dcm()
882 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX); sd_reset_dcm()
888 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, sd_reset_dcm()
894 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX); sd_reset_dcm()
926 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, sd_change_phase()
932 retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F, sd_change_phase()
938 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, sd_change_phase()
944 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, sd_change_phase()
950 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0); sd_change_phase()
962 retval = rtsx_write_register(chip, SD_VP_CTL, sd_change_phase()
970 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, sd_change_phase()
977 retval = rtsx_write_register(chip, CLK_CTL, sd_change_phase()
984 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, sd_change_phase()
1015 retval = rtsx_write_register(chip, SD_DCMPS_CTL, sd_change_phase()
1022 retval = rtsx_write_register(chip, SD_VP_CTL, sd_change_phase()
1029 retval = rtsx_write_register(chip, CLK_CTL, sd_change_phase()
1040 retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); sd_change_phase()
1054 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); sd_change_phase()
1055 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0); sd_change_phase()
1294 retval = rtsx_write_register(chip, OCPPARA2, sd_check_switch_mode()
1301 retval = rtsx_write_register(chip, CARD_PWR_CTL, sd_check_switch_mode()
1476 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, sd_switch_function()
1550 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0); sd_switch_function()
1704 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, sd_sdr_tuning_tx_cmd()
1715 rtsx_write_register(chip, SD_CFG3, sd_sdr_tuning_tx_cmd()
1722 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, sd_sdr_tuning_tx_cmd()
1761 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, sd_ddr_tuning_tx_cmd()
1778 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); sd_ddr_tuning_tx_cmd()
1783 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, sd_ddr_tuning_tx_cmd()
1984 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, sd_ddr_pre_tuning_tx()
1995 rtsx_write_register(chip, SD_CFG3, sd_ddr_pre_tuning_tx()
2013 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, sd_ddr_pre_tuning_tx()
2070 rtsx_write_register(chip, SD_CFG3, sd_tuning_tx()
2262 retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40); sd_prepare_reset()
2268 retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, sd_prepare_reset()
2289 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, sd_pull_ctl_disable()
2295 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, sd_pull_ctl_disable()
2301 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, sd_pull_ctl_disable()
2307 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, sd_pull_ctl_disable()
2313 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, sd_pull_ctl_disable()
2319 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, sd_pull_ctl_disable()
2327 retval = rtsx_write_register(chip, CARD_PULL_CTL1, sd_pull_ctl_disable()
2333 retval = rtsx_write_register(chip, CARD_PULL_CTL2, sd_pull_ctl_disable()
2339 retval = rtsx_write_register(chip, CARD_PULL_CTL3, sd_pull_ctl_disable()
2345 retval = rtsx_write_register(chip, CARD_PULL_CTL4, sd_pull_ctl_disable()
2424 retval = rtsx_write_register(chip, FPGA_PULL_CTL, sd_init_power()
2451 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, sd_init_power()
2465 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01); sd_dummy_clock()
2471 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0); sd_dummy_clock()
2885 retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07, reset_sd()
2960 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, reset_sd()
2966 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, reset_sd()
3007 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02); mmc_test_switch_bus()
3017 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); mmc_test_switch_bus()
3022 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); mmc_test_switch_bus()
3426 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, reset_mmc()
3432 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, reset_mmc()
3473 retval = rtsx_write_register(chip, FPGA_PULL_CTL, reset_sd_card()
3537 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); reset_sd_card()
3542 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); reset_sd_card()
3603 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); reset_mmc_only()
3608 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); reset_mmc_only()
3684 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); sd_stop_seq_mode()
3811 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); sd_rw()
4396 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, sd_execute_no_data()
4404 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, sd_execute_no_data()
4413 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); sd_execute_no_data()
4691 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); sd_execute_read_data()
4697 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); sd_execute_read_data()
4811 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, sd_execute_write_data()
4819 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, sd_execute_write_data()
4828 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); sd_execute_write_data()
5028 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); sd_execute_write_data()
5034 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); sd_execute_write_data()
5251 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); sd_power_off_card3v3()
5274 retval = rtsx_write_register(chip, FPGA_PULL_CTL, sd_power_off_card3v3()
H A Dxd.c419 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, xd_pull_ctl_disable()
425 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, xd_pull_ctl_disable()
431 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, xd_pull_ctl_disable()
437 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, xd_pull_ctl_disable()
443 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, xd_pull_ctl_disable()
449 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, xd_pull_ctl_disable()
457 retval = rtsx_write_register(chip, CARD_PULL_CTL1, xd_pull_ctl_disable()
463 retval = rtsx_write_register(chip, CARD_PULL_CTL2, xd_pull_ctl_disable()
469 retval = rtsx_write_register(chip, CARD_PULL_CTL3, xd_pull_ctl_disable()
475 retval = rtsx_write_register(chip, CARD_PULL_CTL4, xd_pull_ctl_disable()
1222 retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01, xd_copy_page()
1268 rtsx_write_register(chip, xd_copy_page()
1271 rtsx_write_register(chip, xd_copy_page()
2291 retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); xd_power_off_card3v3()
2314 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF); xd_power_off_card3v3()
H A Dms.c434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, ms_pull_ctl_disable()
440 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, ms_pull_ctl_disable()
446 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, ms_pull_ctl_disable()
452 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, ms_pull_ctl_disable()
458 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, ms_pull_ctl_disable()
464 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, ms_pull_ctl_disable()
472 retval = rtsx_write_register(chip, CARD_PULL_CTL1, ms_pull_ctl_disable()
478 retval = rtsx_write_register(chip, CARD_PULL_CTL2, ms_pull_ctl_disable()
484 retval = rtsx_write_register(chip, CARD_PULL_CTL3, ms_pull_ctl_disable()
490 retval = rtsx_write_register(chip, CARD_PULL_CTL4, ms_pull_ctl_disable()
578 retval = rtsx_write_register(chip, FPGA_PULL_CTL, ms_prepare_reset()
610 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, ms_prepare_reset()
618 retval = rtsx_write_register(chip, MS_CFG, 0xFF, ms_prepare_reset()
625 retval = rtsx_write_register(chip, MS_CFG, 0xFF, ms_prepare_reset()
632 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, ms_prepare_reset()
638 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, ms_prepare_reset()
849 retval = rtsx_write_register(chip, MS_CFG, 0x98, ms_switch_8bit_bus()
917 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); ms_pro_reset_flow()
922 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, ms_pro_reset_flow()
2358 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); reset_ms()
2363 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); reset_ms()
2376 retval = rtsx_write_register(chip, MS_CFG, reset_ms()
2920 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); mspro_stop_seq_mode()
3024 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); mspro_rw_multi_sector()
3133 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, mspro_read_format_progress()
3181 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); mspro_read_format_progress()
4727 rtsx_write_register(chip, MS_CFG, ms_cleanup_work()
4757 retval = rtsx_write_register(chip, FPGA_PULL_CTL, ms_power_off_card3v3()
4765 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); ms_power_off_card3v3()
H A Drtsx_card.h1066 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0x0F, 0x0F); card_power_off_all()
1077 rtsx_write_register(chip, CARD_STOP, XD_STOP | XD_CLR_ERR, rtsx_clear_xd_error()
1083 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, rtsx_clear_sd_error()
1089 rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, rtsx_clear_ms_error()
1095 rtsx_write_register(chip, CARD_STOP, SPI_STOP | SPI_CLR_ERR, rtsx_clear_spi_error()
H A Drtsx_scsi.c1335 retval = rtsx_write_register(chip, addr + i, 0xFF, buf[i]); write_mem()
1819 retval = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0); set_chip_mode()
1841 retval = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0x77); set_chip_mode()
2321 retval = rtsx_write_register(chip, PWR_GATE_CTRL, write_efuse()
2339 retval = rtsx_write_register(chip, PWR_GATE_CTRL, write_efuse()
2380 retval = rtsx_write_register(chip, PWR_GATE_CTRL, write_efuse()
2395 retval = rtsx_write_register(chip, PWR_GATE_CTRL, write_efuse()
2791 rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir & 0x06); spi_vendor_cmd()
2823 rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir); spi_vendor_cmd()
2830 rtsx_write_register(chip, CARD_GPIO_DIR, 0x07, gpio_dir); spi_vendor_cmd()
H A Drtsx.c378 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00); rtsx_resume()
H A Drtsx_chip.h963 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data);

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