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Searched refs:rtsx_add_cmd (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/staging/rts5208/
Dspi.c117 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); in sf_polling_status()
118 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, in sf_polling_status()
120 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, in sf_polling_status()
144 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_enable_write()
145 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, in sf_enable_write()
147 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, in sf_enable_write()
149 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, in sf_enable_write()
173 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_disable_write()
174 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, in sf_disable_write()
176 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, in sf_disable_write()
[all …]
Dxd.c98 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); in xd_read_id()
99 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, in xd_read_id()
101 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, in xd_read_id()
105 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); in xd_read_id()
129 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); in xd_assign_phy_addr()
130 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); in xd_assign_phy_addr()
131 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, in xd_assign_phy_addr()
133 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, in xd_assign_phy_addr()
135 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, in xd_assign_phy_addr()
140 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); in xd_assign_phy_addr()
[all …]
Dsd.c148 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
150 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
151 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
152 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
154 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
155 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
157 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
159 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
165 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
[all …]
Dms.c62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_tpc()
63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); in ms_transfer_tpc()
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); in ms_transfer_tpc()
65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, in ms_transfer_tpc()
68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, in ms_transfer_tpc()
70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, in ms_transfer_tpc()
73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); in ms_transfer_tpc()
137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_data()
138 rtsx_add_cmd(chip, WRITE_REG_CMD, in ms_transfer_data()
140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); in ms_transfer_data()
[all …]
Drtsx_card.c681 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
682 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); in switch_ssc_clock()
683 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in switch_ssc_clock()
684 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth); in switch_ssc_clock()
685 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); in switch_ssc_clock()
686 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in switch_ssc_clock()
688 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
690 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
863 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT); in trans_dma_enable()
865 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24)); in trans_dma_enable()
[all …]
Drtsx_transport.h44 void rtsx_add_cmd(struct rtsx_chip *chip,
Drtsx_chip.c2330 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); in rtsx_read_ppbuf()
2346 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); in rtsx_read_ppbuf()
2378 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, in rtsx_write_ppbuf()
2394 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, in rtsx_write_ppbuf()
Drtsx_transport.c204 void rtsx_add_cmd(struct rtsx_chip *chip, in rtsx_add_cmd() function
Drtsx_scsi.c1897 rtsx_add_cmd(chip, cmd_type, addr, mask, value); in rw_mem_cmd_buf()