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Searched refs:rd32 (Results 1 – 59 of 59) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/intel/igb/
De1000_mac.c78 reg = rd32(E1000_STATUS); in igb_get_bus_info_pcie()
475 rd32(E1000_CRCERRS); in igb_clear_hw_cntrs_base()
476 rd32(E1000_SYMERRS); in igb_clear_hw_cntrs_base()
477 rd32(E1000_MPC); in igb_clear_hw_cntrs_base()
478 rd32(E1000_SCC); in igb_clear_hw_cntrs_base()
479 rd32(E1000_ECOL); in igb_clear_hw_cntrs_base()
480 rd32(E1000_MCC); in igb_clear_hw_cntrs_base()
481 rd32(E1000_LATECOL); in igb_clear_hw_cntrs_base()
482 rd32(E1000_COLC); in igb_clear_hw_cntrs_base()
483 rd32(E1000_DC); in igb_clear_hw_cntrs_base()
[all …]
De1000_82575.c91 reg = rd32(E1000_MDIC); in igb_sgmii_uses_mdio_82575()
99 reg = rd32(E1000_MDICNFG); in igb_sgmii_uses_mdio_82575()
187 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_init_phy_params_82575()
223 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> in igb_init_phy_params_82575()
319 u32 eecd = rd32(E1000_EECD); in igb_init_nvm_params_82575()
435 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) in igb_init_mac_params_82575()
484 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_set_sfp_media_type_82575()
609 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_get_invariants_82575()
837 mdic = rd32(E1000_MDIC); in igb_get_phy_id_82575()
846 mdic = rd32(E1000_MDICNFG); in igb_get_phy_id_82575()
[all …]
Digb_ethtool.c146 status = rd32(E1000_STATUS); in igb_get_settings()
462 regs_buff[0] = rd32(E1000_CTRL); in igb_get_regs()
463 regs_buff[1] = rd32(E1000_STATUS); in igb_get_regs()
464 regs_buff[2] = rd32(E1000_CTRL_EXT); in igb_get_regs()
465 regs_buff[3] = rd32(E1000_MDIC); in igb_get_regs()
466 regs_buff[4] = rd32(E1000_SCTL); in igb_get_regs()
467 regs_buff[5] = rd32(E1000_CONNSW); in igb_get_regs()
468 regs_buff[6] = rd32(E1000_VET); in igb_get_regs()
469 regs_buff[7] = rd32(E1000_LEDCTL); in igb_get_regs()
470 regs_buff[8] = rd32(E1000_PBA); in igb_get_regs()
[all …]
Digb_ptp.c87 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82576()
88 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82576()
108 rd32(E1000_SYSTIMR); in igb_ptp_read_82580()
109 lo = rd32(E1000_SYSTIML); in igb_ptp_read_82580()
110 hi = rd32(E1000_SYSTIMH); in igb_ptp_read_82580()
129 rd32(E1000_SYSTIMR); in igb_ptp_read_i210()
130 nsec = rd32(E1000_SYSTIML); in igb_ptp_read_i210()
131 sec = rd32(E1000_SYSTIMH); in igb_ptp_read_i210()
386 ctrl = rd32(E1000_CTRL); in igb_pin_extts()
387 ctrl_ext = rd32(E1000_CTRL_EXT); in igb_pin_extts()
[all …]
Digb_main.c307 regs[n] = rd32(E1000_RDLEN(n)); in igb_regdump()
311 regs[n] = rd32(E1000_RDH(n)); in igb_regdump()
315 regs[n] = rd32(E1000_RDT(n)); in igb_regdump()
319 regs[n] = rd32(E1000_RXDCTL(n)); in igb_regdump()
323 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
327 regs[n] = rd32(E1000_RDBAH(n)); in igb_regdump()
331 regs[n] = rd32(E1000_RDBAL(n)); in igb_regdump()
335 regs[n] = rd32(E1000_TDBAH(n)); in igb_regdump()
339 regs[n] = rd32(E1000_TDLEN(n)); in igb_regdump()
343 regs[n] = rd32(E1000_TDH(n)); in igb_regdump()
[all …]
De1000_i210.c50 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
66 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
83 swsm = rd32(E1000_SWSM); in igb_get_hw_semaphore_i210()
87 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI) in igb_get_hw_semaphore_i210()
151 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_acquire_swfw_sync_i210()
190 swfw_sync = rd32(E1000_SW_FW_SYNC); in igb_release_swfw_sync_i210()
274 rd32(E1000_SRWR)) { in igb_write_nvm_srwr()
352 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_word_i210()
477 invm_dword = rd32(E1000_INVM_DATA_REG(i)); in igb_read_invm_version()
653 reg = rd32(E1000_EECD); in igb_pool_flash_update_done_i210()
[all …]
De1000_nvm.c72 u32 eecd = rd32(E1000_EECD); in igb_shift_out_eec_bits()
117 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
126 eecd = rd32(E1000_EECD); in igb_shift_in_eec_bits()
154 reg = rd32(E1000_EERD); in igb_poll_eerd_eewr_done()
156 reg = rd32(E1000_EEWR); in igb_poll_eerd_eewr_done()
179 u32 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
185 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
191 eecd = rd32(E1000_EECD); in igb_acquire_nvm()
214 u32 eecd = rd32(E1000_EECD); in igb_standby_nvm()
239 eecd = rd32(E1000_EECD); in e1000_stop_nvm()
[all …]
De1000_mbx.c244 u32 mbvficr = rd32(E1000_MBVFICR); in igb_check_for_bit_pf()
302 u32 vflre = rd32(E1000_VFLRE); in igb_check_for_rst_pf()
330 p2v_mailbox = rd32(E1000_P2VMAILBOX(vf_number)); in igb_obtain_mbx_lock_pf()
De1000_regs.h381 #define rd32(reg) (igb_rd32(hw, reg)) macro
383 #define wrfl() ((void)rd32(E1000_STATUS))
De1000_phy.c62 manc = rd32(E1000_MANC); in igb_check_reset_block()
157 mdic = rd32(E1000_MDIC); in igb_read_phy_reg_mdic()
214 mdic = rd32(E1000_MDIC); in igb_write_phy_reg_mdic()
260 i2ccmd = rd32(E1000_I2CCMD); in igb_read_phy_reg_i2c()
317 i2ccmd = rd32(E1000_I2CCMD); in igb_write_phy_reg_i2c()
369 data_local = rd32(E1000_I2CCMD); in igb_read_sfp_data_byte()
1356 ctrl = rd32(E1000_CTRL); in igb_phy_force_speed_duplex_setup()
2094 ctrl = rd32(E1000_CTRL); in igb_phy_hw_reset()
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
Di40e_ptp.c66 lo = rd32(hw, I40E_PRTTSYN_TIME_L); in i40e_ptp_read()
67 hi = rd32(hw, I40E_PRTTSYN_TIME_H); in i40e_ptp_read()
257 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_rx_hang()
285 rd32(hw, I40E_PRTTSYN_RXTIME_H(0)); in i40e_ptp_rx_hang()
286 rd32(hw, I40E_PRTTSYN_RXTIME_H(1)); in i40e_ptp_rx_hang()
287 rd32(hw, I40E_PRTTSYN_RXTIME_H(2)); in i40e_ptp_rx_hang()
288 rd32(hw, I40E_PRTTSYN_RXTIME_H(3)); in i40e_ptp_rx_hang()
319 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L); in i40e_ptp_tx_hwtstamp()
320 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H); in i40e_ptp_tx_hwtstamp()
357 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1); in i40e_ptp_rx_hwtstamp()
[all …]
Di40e_diag.c43 orig_val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
47 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
57 val = rd32(hw, reg); in i40e_diag_reg_pattern_test()
Di40e_lan_hmc.c128 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
131 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ); in i40e_init_lan_hmc()
148 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX); in i40e_init_lan_hmc()
154 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ); in i40e_init_lan_hmc()
171 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX); in i40e_init_lan_hmc()
177 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ); in i40e_init_lan_hmc()
194 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX); in i40e_init_lan_hmc()
200 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ); in i40e_init_lan_hmc()
Di40e_adminq.c318 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
350 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
685 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
687 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
721 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
761 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command()
967 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK); in i40e_clean_arq_element()
Di40e_nvm.c49 gens = rd32(hw, I40E_GLNVM_GENS); in i40e_init_nvm()
56 fla = rd32(hw, I40E_GLNVM_FLA); in i40e_init_nvm()
91 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
106 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_acquire_nvm()
154 srctl = rd32(hw, I40E_GLNVM_SRCTL); in i40e_poll_sr_srctl_done_bit()
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA); in i40e_read_nvm_word_srctl()
1008 gtime = rd32(hw, I40E_GLVFGEN_TIMER); in i40e_nvmupd_state_writing()
Di40e_osdep.h47 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
Di40e_common.c351 return !!(rd32(hw, hw->aq.asq.len) & in i40e_check_asq_alive()
936 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) in i40e_init_shared_code()
939 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >> in i40e_init_shared_code()
941 func_rid = rd32(hw, I40E_PF_FUNC_RID); in i40e_init_shared_code()
1077 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block)); in i40e_pre_tx_queue_cfg()
1246 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) & in i40e_pf_reset()
1250 reg = rd32(hw, I40E_GLGEN_RSTAT); in i40e_pf_reset()
1262 reg = rd32(hw, I40E_GLNVM_ULD); in i40e_pf_reset()
1287 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
1291 reg = rd32(hw, I40E_PFGEN_CTRL); in i40e_pf_reset()
[all …]
Di40e_main.c351 val = rd32(&pf->hw, in i40e_tx_timeout()
355 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); in i40e_tx_timeout()
563 new_data = rd32(hw, loreg); in i40e_stat_update48()
564 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; in i40e_stat_update48()
590 new_data = rd32(hw, reg); in i40e_stat_update32()
1162 val = rd32(hw, I40E_PRTPM_EEE_STAT); in i40e_update_pf_stats()
3147 rd32(hw, I40E_PFINT_ICR0); /* read to clear */ in i40e_enable_misc_int_causes()
3420 icr0 = rd32(hw, I40E_PFINT_ICR0); in i40e_intr()
3421 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); in i40e_intr()
3445 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)); in i40e_intr()
[all …]
Di40e_virtchnl_pf.c343 reg = rd32(hw, I40E_GLINT_CTL); in i40e_config_irq_link_list()
767 reg = rd32(hw, I40E_PF_PCI_CIAD); in i40e_quiesce_vf_pci()
801 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); in i40e_reset_vf()
821 reg = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_id)); in i40e_reset_vf()
836 reg = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_id)); in i40e_reset_vf()
2017 reg = rd32(hw, I40E_PFINT_ICR0_ENA); in i40e_vc_process_vflr_event()
2028 reg = rd32(hw, I40E_GLGEN_VFLRSTAT(reg_idx)); in i40e_vc_process_vflr_event()
Di40e_dcb_nl.c42 val = rd32(hw, I40E_PRTDCB_GENC); in i40e_get_pfc_delay()
Di40e_ethtool.c972 reg_buf[ri++] = rd32(hw, reg); in i40e_get_regs()
1076 val = (rd32(hw, I40E_GLPCI_LBARCTRL) in i40e_get_eeprom_len()
2148 u64 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) | in i40e_set_rss_hash_opt()
2149 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32); in i40e_set_rss_hash_opt()
2626 reg_val = rd32(hw, I40E_PFQF_HLUT(i)); in i40e_get_rxfh()
2635 reg_val = rd32(hw, I40E_PFQF_HKEY(i)); in i40e_get_rxfh()
Di40e_fcoe.c298 val = rd32(hw, I40E_PFQF_HENA(1)); in i40e_init_pf_fcoe()
320 val = rd32(hw, I40E_GLFCOE_RCTL); in i40e_init_pf_fcoe()
Di40e_dcb.c45 reg = rd32(hw, I40E_PRTDCB_GENS); in i40e_get_dcbx_status()
Di40e_debugfs.c1501 value = rd32(&pf->hw, address); in i40e_dbg_command_write()
1521 value = rd32(&pf->hw, address); in i40e_dbg_command_write()
Di40e_txrx.c1948 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) | in i40e_napi_poll()
1952 qval = rd32(hw, I40E_QINT_TQCTL(0)) | in i40e_napi_poll()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/core/
Dgpuobj.c68 .rd32 = nvkm_gpuobj_rd32_fast,
75 .rd32 = nvkm_gpuobj_heap_rd32,
119 .rd32 = nvkm_gpuobj_rd32_fast,
126 .rd32 = nvkm_gpuobj_rd32,
Dobject.c72 if (likely(object->func->rd32)) in nvkm_object_rd32()
73 return object->func->rd32(object, addr, data); in nvkm_object_rd32()
Doproxy.c176 .rd32 = nvkm_oproxy_rd32,
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/
Dmemory.h26 u32 (*rd32)(struct nvkm_memory *, u64 offset); member
45 #define nvkm_ro32(o,a) (o)->func->rd32((o), (a))
Dgpuobj.h29 u32 (*rd32)(struct nvkm_gpuobj *, u32 offset); member
Dobject.h33 int (*rd32)(struct nvkm_object *, u64 addr, u32 *data); member
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dnv4c.c28 .rd32 = nv40_pci_rd32,
Dg94.c29 .rd32 = nv40_pci_rd32,
Dgf100.c35 .rd32 = nv40_pci_rd32,
Dbase.c34 return pci->func->rd32(pci, addr); in nvkm_pci_rd32()
52 u32 data = pci->func->rd32(pci, addr); in nvkm_pci_mask()
Dg84.c54 .rd32 = nv40_pci_rd32,
Dnv46.c41 .rd32 = nv40_pci_rd32,
Dpriv.h11 u32 (*rd32)(struct nvkm_pci *, u16 addr); member
Dnv04.c49 .rd32 = nv04_pci_rd32,
Dnv40.c55 .rd32 = nv40_pci_rd32,
/linux-4.4.14/drivers/net/ethernet/intel/i40evf/
Di40evf_ethtool.c376 u64 hena = (u64)rd32(hw, I40E_VFQF_HENA(0)) | in i40evf_get_rss_hash_opts()
377 ((u64)rd32(hw, I40E_VFQF_HENA(1)) << 32); in i40evf_get_rss_hash_opts()
463 u64 hena = (u64)rd32(hw, I40E_VFQF_HENA(0)) | in i40evf_set_rss_hash_opt()
464 ((u64)rd32(hw, I40E_VFQF_HENA(1)) << 32); in i40evf_set_rss_hash_opt()
648 hlut_val = rd32(hw, I40E_VFQF_HLUT(i)); in i40evf_get_rxfh()
Di40e_adminq.c305 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
337 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
617 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
619 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
654 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40evf_asq_done()
694 val = rd32(hw, hw->aq.asq.head); in i40evf_asq_send_command()
901 ntu = (rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK); in i40evf_clean_arq_element()
Di40evf_main.c192 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_misc_irq_disable()
210 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_misc_irq_enable()
230 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_irq_disable()
265 dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTL01); in i40evf_fire_sw_int()
273 dyn_ctl = rd32(hw, I40E_VFINT_DYN_CTLN1(i - 1)); in i40evf_fire_sw_int()
295 rd32(hw, I40E_VFGEN_RSTAT); in i40evf_irq_enable()
311 rd32(hw, I40E_VFINT_ICR01); in i40evf_msix_aq()
312 rd32(hw, I40E_VFINT_ICR0_ENA1); in i40evf_msix_aq()
315 val = rd32(hw, I40E_VFINT_DYN_CTL01) | in i40evf_msix_aq()
1469 reg_val = rd32(hw, I40E_VFGEN_RSTAT) & in i40evf_watchdog_task()
[all …]
Di40e_osdep.h46 #define rd32(a, reg) readl((a)->hw_addr + (reg)) macro
Di40e_common.c351 return !!(rd32(hw, hw->aq.asq.len) & in i40evf_check_asq_alive()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dbase.c115 .rd32 = nvkm_instobj_rd32,
168 .rd32 = nvkm_instobj_rd32_slow,
226 return imem->func->rd32(imem, addr); in nvkm_instmem_rd32()
Dpriv.h10 u32 (*rd32)(struct nvkm_instmem *, u32 addr); member
Dnv04.c111 .rd32 = nv04_instobj_rd32,
209 .rd32 = nv04_instmem_rd32,
Dnv40.c110 .rd32 = nv40_instobj_rd32,
226 .rd32 = nv40_instmem_rd32,
Dgk20a.c371 .rd32 = gk20a_instobj_rd32,
384 .rd32 = gk20a_instobj_rd32,
Dnv50.c187 .rd32 = nv50_instobj_rd32,
/linux-4.4.14/drivers/net/fjes/
Dfjes_hw.c78 dctl.reg = rd32(XSCT_DCTL); in fjes_hw_reset()
81 dctl.reg = rd32(XSCT_DCTL); in fjes_hw_reset()
92 info.reg = rd32(XSCT_MAX_EP); in fjes_hw_get_max_epid()
101 info.reg = rd32(XSCT_OWNER_EPID); in fjes_hw_get_my_epid()
374 cr.reg = rd32(XSCT_CR); in fjes_hw_issue_request_command()
378 cs.reg = rd32(XSCT_CS); in fjes_hw_issue_request_command()
382 cs.reg = rd32(XSCT_CS); in fjes_hw_issue_request_command()
662 cur_is = rd32(XSCT_IS); in fjes_hw_capture_interrupt_status()
Dfjes_regs.h140 #define rd32(reg) (fjes_hw_rd32(hw, reg)) macro
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Di2c_.fuc291 call(rd32)
298 call(rd32)
Dmacros.fuc229 */ call(rd32) /*
Dkernel.fuc52 rd32:
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dchannv50.c256 .rd32 = nv50_disp_chan_rd32,
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/device/
Duser.c308 .rd32 = nvkm_udevice_rd32,
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dchan.c342 .rd32 = nvkm_fifo_chan_rd32,