/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | r600_cs.c | 850 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); r600_cs_common_vline_parse() 866 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { r600_cs_common_vline_parse() 871 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { r600_cs_common_vline_parse() 885 header = radeon_get_ib_value(p, h_idx); r600_cs_common_vline_parse() 886 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); r600_cs_common_vline_parse() 1008 /*tmp =radeon_get_ib_value(p, idx); r600_cs_check_reg() 1026 track->sq_config = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1029 track->db_depth_control = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1041 track->db_depth_info = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1052 track->db_depth_info = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1057 track->db_depth_view = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1061 track->db_depth_size = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1066 track->vgt_strmout_en = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1070 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1084 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; r600_cs_check_reg() 1096 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; r600_cs_check_reg() 1109 track->cb_target_mask = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1113 track->cb_shader_mask = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1116 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); r600_cs_check_reg() 1122 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); r600_cs_check_reg() 1142 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1152 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1165 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1177 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1261 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1281 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; r600_cs_check_reg() 1295 track->db_offset = radeon_get_ib_value(p, idx) << 8; r600_cs_check_reg() 1308 track->htile_offset = radeon_get_ib_value(p, idx) << 8; r600_cs_check_reg() 1314 track->htile_surface = radeon_get_ib_value(p, idx); r600_cs_check_reg() 1390 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; r600_cs_check_reg() 1494 word0 = radeon_get_ib_value(p, idx + 0); r600_check_texture_resource() 1501 word1 = radeon_get_ib_value(p, idx + 1); r600_check_texture_resource() 1502 word2 = radeon_get_ib_value(p, idx + 2) << 8; r600_check_texture_resource() 1503 word3 = radeon_get_ib_value(p, idx + 3) << 8; r600_check_texture_resource() 1504 word4 = radeon_get_ib_value(p, idx + 4); r600_check_texture_resource() 1505 word5 = radeon_get_ib_value(p, idx + 5); r600_check_texture_resource() 1641 idx_value = radeon_get_ib_value(p, idx); r600_packet3_check() 1655 tmp = radeon_get_ib_value(p, idx + 1); r600_packet3_check() 1716 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); r600_packet3_check() 1767 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + r600_packet3_check() 1768 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); r600_packet3_check() 1785 command = radeon_get_ib_value(p, idx+4); r600_packet3_check() 1803 tmp = radeon_get_ib_value(p, idx) + r600_packet3_check() 1804 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); r600_packet3_check() 1833 tmp = radeon_get_ib_value(p, idx+2) + r600_packet3_check() 1834 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); r600_packet3_check() 1855 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || r600_packet3_check() 1856 radeon_get_ib_value(p, idx + 2) != 0) { r600_packet3_check() 1879 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + r600_packet3_check() 1880 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); r600_packet3_check() 1901 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + r600_packet3_check() 1902 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); r600_packet3_check() 1957 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { r600_packet3_check() 1983 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), r600_packet3_check() 1984 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), r600_packet3_check() 2000 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); r600_packet3_check() 2001 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; r600_packet3_check() 2107 offset = radeon_get_ib_value(p, idx+1) << 8; r600_packet3_check() 2145 offset = radeon_get_ib_value(p, idx+1); r600_packet3_check() 2146 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; r600_packet3_check() 2164 offset = radeon_get_ib_value(p, idx+3); r600_packet3_check() 2165 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; r600_packet3_check() 2189 offset = radeon_get_ib_value(p, idx+0); r600_packet3_check() 2190 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; r600_packet3_check() 2218 offset = radeon_get_ib_value(p, idx+1); r600_packet3_check() 2219 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; r600_packet3_check() 2230 reg = radeon_get_ib_value(p, idx+1) << 2; r600_packet3_check() 2242 offset = radeon_get_ib_value(p, idx+3); r600_packet3_check() 2243 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; r600_packet3_check() 2254 reg = radeon_get_ib_value(p, idx+3) << 2; r600_packet3_check() 2490 header = radeon_get_ib_value(p, idx); r600_dma_cs_parse() 2503 dst_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2509 dst_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2510 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; r600_dma_cs_parse() 2534 idx_value = radeon_get_ib_value(p, idx + 2); r600_dma_cs_parse() 2538 src_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2542 dst_offset = radeon_get_ib_value(p, idx+5); r600_dma_cs_parse() 2543 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; r600_dma_cs_parse() 2548 src_offset = radeon_get_ib_value(p, idx+5); r600_dma_cs_parse() 2549 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; r600_dma_cs_parse() 2553 dst_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2560 src_offset = radeon_get_ib_value(p, idx+2); r600_dma_cs_parse() 2561 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; r600_dma_cs_parse() 2562 dst_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2563 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; r600_dma_cs_parse() 2571 src_offset = radeon_get_ib_value(p, idx+2); r600_dma_cs_parse() 2572 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; r600_dma_cs_parse() 2573 dst_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2574 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; r600_dma_cs_parse() 2604 dst_offset = radeon_get_ib_value(p, idx+1); r600_dma_cs_parse() 2605 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; r600_dma_cs_parse()
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H A D | evergreen_cs.c | 763 texdw[0] = radeon_get_ib_value(p, idx + 0); evergreen_cs_track_validate_texture() 764 texdw[1] = radeon_get_ib_value(p, idx + 1); evergreen_cs_track_validate_texture() 765 texdw[2] = radeon_get_ib_value(p, idx + 2); evergreen_cs_track_validate_texture() 766 texdw[3] = radeon_get_ib_value(p, idx + 3); evergreen_cs_track_validate_texture() 767 texdw[4] = radeon_get_ib_value(p, idx + 4); evergreen_cs_track_validate_texture() 768 texdw[5] = radeon_get_ib_value(p, idx + 5); evergreen_cs_track_validate_texture() 769 texdw[6] = radeon_get_ib_value(p, idx + 6); evergreen_cs_track_validate_texture() 770 texdw[7] = radeon_get_ib_value(p, idx + 7); evergreen_cs_track_validate_texture() 1132 /*tmp =radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1152 track->db_depth_control = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1170 track->db_z_info = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1198 track->db_s_info = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1202 track->db_depth_view = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1206 track->db_depth_size = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1210 track->db_depth_slice = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1220 track->db_z_read_offset = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1232 track->db_z_write_offset = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1244 track->db_s_read_offset = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1256 track->db_s_write_offset = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1262 track->vgt_strmout_config = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1266 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1280 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; evergreen_cs_handle_reg() 1291 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; evergreen_cs_handle_reg() 1303 track->cb_target_mask = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1307 track->cb_shader_mask = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1316 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; evergreen_cs_handle_reg() 1325 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; evergreen_cs_handle_reg() 1337 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1345 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1357 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1375 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1397 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1405 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1417 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1426 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1533 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1544 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1561 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1577 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1589 track->htile_offset = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1596 track->htile_surface = radeon_get_ib_value(p, idx); evergreen_cs_handle_reg() 1738 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; evergreen_cs_handle_reg() 1786 idx_value = radeon_get_ib_value(p, idx); evergreen_packet3_check() 1800 tmp = radeon_get_ib_value(p, idx + 1); evergreen_packet3_check() 1866 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); evergreen_packet3_check() 1901 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); evergreen_packet3_check() 1928 radeon_get_ib_value(p, idx+1) + evergreen_packet3_check() 1929 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); evergreen_packet3_check() 2101 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + evergreen_packet3_check() 2102 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); evergreen_packet3_check() 2119 command = radeon_get_ib_value(p, idx+4); evergreen_packet3_check() 2121 info = radeon_get_ib_value(p, idx+1); evergreen_packet3_check() 2154 tmp = radeon_get_ib_value(p, idx) + evergreen_packet3_check() 2155 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); evergreen_packet3_check() 2192 tmp = radeon_get_ib_value(p, idx+2) + evergreen_packet3_check() 2193 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); evergreen_packet3_check() 2218 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || evergreen_packet3_check() 2219 radeon_get_ib_value(p, idx + 2) != 0) { evergreen_packet3_check() 2242 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + evergreen_packet3_check() 2243 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); evergreen_packet3_check() 2264 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + evergreen_packet3_check() 2265 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); evergreen_packet3_check() 2286 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + evergreen_packet3_check() 2287 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); evergreen_packet3_check() 2345 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { evergreen_packet3_check() 2409 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); evergreen_packet3_check() 2410 size = radeon_get_ib_value(p, idx+1+(i*8)+1); evergreen_packet3_check() 2491 offset = radeon_get_ib_value(p, idx+1); evergreen_packet3_check() 2492 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; evergreen_packet3_check() 2510 offset = radeon_get_ib_value(p, idx+3); evergreen_packet3_check() 2511 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; evergreen_packet3_check() 2535 offset = radeon_get_ib_value(p, idx+0); evergreen_packet3_check() 2536 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; evergreen_packet3_check() 2564 offset = radeon_get_ib_value(p, idx+1); evergreen_packet3_check() 2565 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; evergreen_packet3_check() 2576 reg = radeon_get_ib_value(p, idx+1) << 2; evergreen_packet3_check() 2591 offset = radeon_get_ib_value(p, idx+3); evergreen_packet3_check() 2592 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; evergreen_packet3_check() 2603 reg = radeon_get_ib_value(p, idx+3) << 2; evergreen_packet3_check() 2762 header = radeon_get_ib_value(p, idx); evergreen_dma_cs_parse() 2777 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2785 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2786 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; evergreen_dma_cs_parse() 2817 src_offset = radeon_get_ib_value(p, idx+2); evergreen_dma_cs_parse() 2818 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; evergreen_dma_cs_parse() 2819 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2820 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; evergreen_dma_cs_parse() 2840 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { evergreen_dma_cs_parse() 2842 src_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2846 dst_offset = radeon_get_ib_value(p, idx + 7); evergreen_dma_cs_parse() 2847 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; evergreen_dma_cs_parse() 2852 src_offset = radeon_get_ib_value(p, idx+7); evergreen_dma_cs_parse() 2853 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; evergreen_dma_cs_parse() 2857 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2876 src_offset = radeon_get_ib_value(p, idx+2); evergreen_dma_cs_parse() 2877 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; evergreen_dma_cs_parse() 2878 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2879 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; evergreen_dma_cs_parse() 2918 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2919 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; evergreen_dma_cs_parse() 2920 dst2_offset = radeon_get_ib_value(p, idx+2); evergreen_dma_cs_parse() 2921 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; evergreen_dma_cs_parse() 2922 src_offset = radeon_get_ib_value(p, idx+3); evergreen_dma_cs_parse() 2923 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; evergreen_dma_cs_parse() 2949 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { evergreen_dma_cs_parse() 2958 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 2960 dst2_offset = radeon_get_ib_value(p, idx+2); evergreen_dma_cs_parse() 2962 src_offset = radeon_get_ib_value(p, idx+8); evergreen_dma_cs_parse() 2963 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; evergreen_dma_cs_parse() 2993 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { evergreen_dma_cs_parse() 3011 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { evergreen_dma_cs_parse() 3020 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 3022 dst2_offset = radeon_get_ib_value(p, idx+2); evergreen_dma_cs_parse() 3024 src_offset = radeon_get_ib_value(p, idx+8); evergreen_dma_cs_parse() 3025 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; evergreen_dma_cs_parse() 3051 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { evergreen_dma_cs_parse() 3053 src_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 3057 dst_offset = radeon_get_ib_value(p, idx+7); evergreen_dma_cs_parse() 3058 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; evergreen_dma_cs_parse() 3063 src_offset = radeon_get_ib_value(p, idx+7); evergreen_dma_cs_parse() 3064 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; evergreen_dma_cs_parse() 3068 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 3098 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { evergreen_dma_cs_parse() 3107 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 3109 dst2_offset = radeon_get_ib_value(p, idx+2); evergreen_dma_cs_parse() 3111 src_offset = radeon_get_ib_value(p, idx+8); evergreen_dma_cs_parse() 3112 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; evergreen_dma_cs_parse() 3145 dst_offset = radeon_get_ib_value(p, idx+1); evergreen_dma_cs_parse() 3146 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; evergreen_dma_cs_parse()
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H A D | radeon_vce.c | 479 offset = radeon_get_ib_value(p, lo); radeon_vce_cs_reloc() 480 idx = radeon_get_ib_value(p, hi); radeon_vce_cs_reloc() 566 uint32_t len = radeon_get_ib_value(p, p->idx); radeon_vce_cs_parse() 567 uint32_t cmd = radeon_get_ib_value(p, p->idx + 1); radeon_vce_cs_parse() 583 handle = radeon_get_ib_value(p, p->idx + 2); radeon_vce_cs_parse() 602 *size = radeon_get_ib_value(p, p->idx + 8) * radeon_vce_cs_parse() 603 radeon_get_ib_value(p, p->idx + 10) * radeon_vce_cs_parse() 639 tmp = radeon_get_ib_value(p, p->idx + 4); radeon_vce_cs_parse()
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H A D | r300.c | 642 idx_value = radeon_get_ib_value(p, idx); r300_packet0_check() 1198 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); r300_packet3_check() 1209 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { r300_packet3_check() 1213 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r300_packet3_check() 1224 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { r300_packet3_check() 1228 track->vap_vf_cntl = radeon_get_ib_value(p, idx); r300_packet3_check() 1236 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r300_packet3_check() 1243 track->vap_vf_cntl = radeon_get_ib_value(p, idx); r300_packet3_check() 1250 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r300_packet3_check() 1257 track->vap_vf_cntl = radeon_get_ib_value(p, idx); r300_packet3_check()
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H A D | r100.c | 1278 value = radeon_get_ib_value(p, idx); r100_reloc_pitch_offset() 1314 c = radeon_get_ib_value(p, idx++) & 0x1F; r100_packet3_load_vbpntr() 1330 idx_value = radeon_get_ib_value(p, idx); r100_packet3_load_vbpntr() 1331 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); r100_packet3_load_vbpntr() 1343 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset); r100_packet3_load_vbpntr() 1356 idx_value = radeon_get_ib_value(p, idx); r100_packet3_load_vbpntr() 1357 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset); r100_packet3_load_vbpntr() 1448 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { r100_cs_packet_parse_vline() 1462 header = radeon_get_ib_value(p, h_idx); r100_cs_packet_parse_vline() 1463 crtc_id = radeon_get_ib_value(p, h_idx + 5); r100_cs_packet_parse_vline() 1567 idx_value = radeon_get_ib_value(p, idx); r100_packet0_check() 1900 value = radeon_get_ib_value(p, idx + 2); r100_cs_track_check_pkt3_indx_buffer() 1936 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset); r100_packet3_check() 1950 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset); r100_packet3_check() 1952 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); r100_packet3_check() 1957 track->max_indx = radeon_get_ib_value(p, idx+1); r100_packet3_check() 1959 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); r100_packet3_check() 1966 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { r100_packet3_check() 1970 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); r100_packet3_check() 1971 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r100_packet3_check() 1979 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { r100_packet3_check() 1983 track->vap_vf_cntl = radeon_get_ib_value(p, idx); r100_packet3_check() 1991 track->vap_vf_cntl = radeon_get_ib_value(p, idx); r100_packet3_check() 1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx); r100_packet3_check() 2005 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r100_packet3_check() 2012 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); r100_packet3_check()
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H A D | radeon_cs.c | 727 header = radeon_get_ib_value(p, idx); radeon_cs_packet_parse() 763 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i)); radeon_cs_packet_parse() 765 printk("\t0x%08x\n", radeon_get_ib_value(p, i)); radeon_cs_packet_parse() 848 idx = radeon_get_ib_value(p, p3reloc.idx + 1); radeon_cs_packet_next_reloc()
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H A D | radeon_uvd.c | 539 offset = radeon_get_ib_value(p, data0); radeon_uvd_cs_reloc() 540 idx = radeon_get_ib_value(p, data1); radeon_uvd_cs_reloc() 555 cmd = radeon_get_ib_value(p, p->idx) >> 1; radeon_uvd_cs_reloc()
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H A D | r200.c | 161 idx_value = radeon_get_ib_value(p, idx); r200_packet0_check()
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H A D | radeon.h | 1103 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) radeon_get_ib_value() function
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