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Searched refs:pll_data (Results 1 – 13 of 13) sorted by relevance

/linux-4.4.14/drivers/clk/keystone/
Dpll.c74 struct clk_pll_data *pll_data; member
83 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc() local
91 if (pll_data->has_pllctrl) { in clk_pllclk_recalc()
92 val = readl(pll_data->pllm); in clk_pllclk_recalc()
93 mult = (val & pll_data->pllm_lower_mask); in clk_pllclk_recalc()
97 val = readl(pll_data->pll_ctl0); in clk_pllclk_recalc()
98 mult |= ((val & pll_data->pllm_upper_mask) in clk_pllclk_recalc()
99 >> pll_data->pllm_upper_shift); in clk_pllclk_recalc()
100 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
102 if (!pll_data->has_pllctrl) in clk_pllclk_recalc()
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/linux-4.4.14/arch/c6x/include/asm/
Dclock.h80 struct pll_data;
92 struct pll_data *pll_data; member
108 struct pll_data { struct
136 extern struct pll_data c6x_soc_pll1;
/linux-4.4.14/arch/arm/mach-davinci/
Dclock.c292 struct pll_data *pll; in clk_sysclk_recalc()
296 if (clk->pll_data) in clk_sysclk_recalc()
305 if (WARN_ON(!clk->parent->pll_data)) in clk_sysclk_recalc()
308 pll = clk->parent->pll_data; in clk_sysclk_recalc()
330 struct pll_data *pll; in davinci_set_sysclk_rate()
335 if (clk->pll_data) in davinci_set_sysclk_rate()
343 if (WARN_ON(!clk->parent->pll_data)) in davinci_set_sysclk_rate()
350 pll = clk->parent->pll_data; in davinci_set_sysclk_rate()
418 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc()
485 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, in davinci_set_pllrate()
[all …]
Dclock.h76 struct pll_data { struct
101 struct pll_data *pll_data; argument
128 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
Ddm646x.c54 static struct pll_data pll1_data = {
59 static struct pll_data pll2_data = {
78 .pll_data = &pll1_data,
154 .pll_data = &pll2_data,
Ddm644x.c45 static struct pll_data pll1_data = {
50 static struct pll_data pll2_data = {
63 .pll_data = &pll1_data,
111 .pll_data = &pll2_data,
Ddm355.c45 static struct pll_data pll1_data = {
51 static struct pll_data pll2_data = {
67 .pll_data = &pll1_data,
145 .pll_data = &pll2_data,
Dda850.c54 static struct pll_data pll0_data = {
69 .pll_data = &pll0_data,
131 static struct pll_data pll1_data = {
140 .pll_data = &pll1_data,
1128 struct pll_data *pll = clk->pll_data; in da850_set_pll0rate()
Ddm365.c56 static struct pll_data pll1_data = {
62 static struct pll_data pll2_data = {
77 .pll_data = &pll1_data,
166 .pll_data = &pll2_data,
Dda830.c40 static struct pll_data pll0_data = {
54 .pll_data = &pll0_data,
/linux-4.4.14/arch/c6x/platforms/
Dpll.c204 static u32 pll_read(struct pll_data *pll, int reg) in pll_read()
212 struct pll_data *pll; in clk_sysclk_recalc()
221 if (WARN_ON(!clk->parent->pll_data)) in clk_sysclk_recalc()
224 pll = clk->parent->pll_data; in clk_sysclk_recalc()
273 struct pll_data *pll = clk->pll_data; in clk_pllclk_recalc()
335 if (clk->pll_data) in __init_clk()
Dplldata.c36 struct pll_data c6x_soc_pll1 = {
42 .pll_data = &c6x_soc_pll1,
172 struct pll_data *pll = &c6x_soc_pll1; in c6455_setup_clocks()
210 struct pll_data *pll = &c6x_soc_pll1; in c6457_setup_clocks()
260 struct pll_data *pll = &c6x_soc_pll1; in c6472_setup_clocks()
309 struct pll_data *pll = &c6x_soc_pll1; in c6474_setup_clocks()
358 struct pll_data *pll = &c6x_soc_pll1; in c6678_setup_clocks()
423 struct pll_data *pll = &c6x_soc_pll1; in c64x_setup_clocks()
/linux-4.4.14/drivers/clk/st/
Dclkgen-pll.c842 struct clkgen_pll_data *pll_data, in clkgen_pll_register() argument
855 init.ops = pll_data->ops; in clkgen_pll_register()
861 pll->data = pll_data; in clkgen_pll_register()
997 struct clkgen_pll_data *pll_data, in clkgen_odf_register() argument
1014 gate->reg = reg + pll_data->odf_gate[odf].offset; in clkgen_odf_register()
1015 gate->bit_idx = pll_data->odf_gate[odf].shift; in clkgen_odf_register()
1025 div->reg = reg + pll_data->odf[odf].offset; in clkgen_odf_register()
1026 div->shift = pll_data->odf[odf].shift; in clkgen_odf_register()
1027 div->width = fls(pll_data->odf[odf].mask); in clkgen_odf_register()