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Searched refs:pipe_bpp (Results 1 – 14 of 14) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_dsi_pll.c316 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) in assert_bpp_mismatch() argument
320 WARN(bpp != pipe_bpp, in assert_bpp_mismatch()
322 bpp, pipe_bpp); in assert_bpp_mismatch()
325 u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) in vlv_get_dsi_pclk() argument
380 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); in vlv_get_dsi_pclk()
382 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_get_dsi_pclk()
387 u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) in bxt_get_dsi_pclk() argument
396 if (!pipe_bpp) { in bxt_get_dsi_pclk()
414 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); in bxt_get_dsi_pclk()
416 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); in bxt_get_dsi_pclk()
Dintel_dsi.h129 extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
130 extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
Dintel_dp_mst.c62 pipe_config->pipe_bpp = 24; in intel_dp_mst_compute_config()
266 pipe_config->pipe_bpp = 18; in intel_dp_mst_enc_get_config()
269 pipe_config->pipe_bpp = 24; in intel_dp_mst_enc_get_config()
272 pipe_config->pipe_bpp = 30; in intel_dp_mst_enc_get_config()
275 pipe_config->pipe_bpp = 36; in intel_dp_mst_enc_get_config()
Dintel_lvds.c189 if (crtc->config->dither && crtc->config->pipe_bpp == 18) in intel_pre_enable_lvds()
322 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
324 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
325 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
Dintel_hdmi.c599 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
604 switch (pipe_bpp) { in gcp_default_phase_possible()
652 if (gcp_default_phase_possible(crtc->config->pipe_bpp, in intel_hdmi_set_gcp_infoframe()
857 if (crtc->config->pipe_bpp > 24) in intel_hdmi_prepare()
1015 if (crtc->config->pipe_bpp > 24 && in ibx_enable_hdmi()
1059 if (crtc->config->pipe_bpp > 24) { in cpt_enable_hdmi()
1071 if (crtc->config->pipe_bpp > 24) { in cpt_enable_hdmi()
1288 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && in intel_hdmi_compute_config()
1305 pipe_config->pipe_bpp = desired_bpp; in intel_hdmi_compute_config()
Dintel_ddi.c1045 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1814 switch (intel_crtc->config->pipe_bpp) { in intel_ddi_set_pipe_settings()
1866 switch (intel_crtc->config->pipe_bpp) { in intel_ddi_enable_transcoder_func()
3133 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
3136 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
3139 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
3142 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
3177 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { in intel_ddi_get_config()
3192 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); in intel_ddi_get_config()
3193 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; in intel_ddi_get_config()
Dintel_dsi.c708 pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); in intel_dsi_get_config()
710 pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); in intel_dsi_get_config()
776 unsigned int bpp = intel_crtc->config->pipe_bpp; in set_dsi_timings()
847 unsigned int bpp = intel_crtc->config->pipe_bpp; in intel_dsi_prepare()
Dintel_crt.c252 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in intel_crt_compute_config()
257 pipe_config->pipe_bpp = 24; in intel_crt_compute_config()
Dintel_display.c6588 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6592 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
6597 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
6598 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
6600 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6616 if (pipe_config->pipe_bpp > 24) in pipe_config_supports_ips()
7848 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) in i9xx_set_pipeconf()
7852 switch (intel_crtc->config->pipe_bpp) { in i9xx_set_pipeconf()
8150 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
8153 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
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Dintel_dp.c1444 bpp = pipe_config->pipe_bpp; in intel_dp_compute_config()
1504 pipe_config->pipe_bpp = bpp; in intel_dp_compute_config()
2339 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { in intel_dp_get_config()
2354 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); in intel_dp_get_config()
2355 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
Dintel_drv.h422 int pipe_bpp; member
Dintel_tv.c929 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
Dintel_panel.c369 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18) in intel_gmch_panel_fitting()
Dintel_sdvo.c1136 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()