6588 					   pipe_config->pipe_bpp);  in ironlake_fdi_compute_config()
6592 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,  in ironlake_fdi_compute_config()
6597 	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {  in ironlake_fdi_compute_config()
6598 		pipe_config->pipe_bpp -= 2*3;  in ironlake_fdi_compute_config()
6600 			      pipe_config->pipe_bpp);  in ironlake_fdi_compute_config()
6616 	if (pipe_config->pipe_bpp > 24)  in pipe_config_supports_ips()
7848 		if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)  in i9xx_set_pipeconf()
7852 		switch (intel_crtc->config->pipe_bpp) {  in i9xx_set_pipeconf()
8150 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
8153 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
8156 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
8620 	switch (intel_crtc->config->pipe_bpp) {  in ironlake_set_pipeconf()
8745 		switch (intel_crtc->config->pipe_bpp) {  in haswell_set_pipeconf()
9280 		pipe_config->pipe_bpp = 18;  in ironlake_get_pipe_config()
9283 		pipe_config->pipe_bpp = 24;  in ironlake_get_pipe_config()
9286 		pipe_config->pipe_bpp = 30;  in ironlake_get_pipe_config()
9289 		pipe_config->pipe_bpp = 36;  in ironlake_get_pipe_config()
11919 	int bpp = pipe_config->pipe_bpp;  in connected_sink_compute_bpp()
11930 		pipe_config->pipe_bpp = connector->base.display_info.bpc*3;  in connected_sink_compute_bpp()
11946 			pipe_config->pipe_bpp = clamp_bpp;  in connected_sink_compute_bpp()
11969 	pipe_config->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
12011 		      pipe_config->pipe_bpp, pipe_config->dither);  in intel_dump_pipe_config()
12311 	pipe_config->dither = pipe_config->pipe_bpp == 6*3;  in intel_modeset_pipe_config()
12313 		      base_bpp, pipe_config->pipe_bpp, pipe_config->dither);  in intel_modeset_pipe_config()
12620 		PIPE_CONF_CHECK_I(pipe_bpp);  in intel_pipe_config_compare()