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Searched refs:oclass (Results 1 – 114 of 114) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dchan.c133 nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_fifo_chan_child_new() argument
136 struct nvkm_engine *engine = oclass->engine; in nvkm_fifo_chan_child_new()
137 struct nvkm_fifo_chan *chan = nvkm_fifo_chan(oclass->parent); in nvkm_fifo_chan_child_new()
144 nvkm_oproxy_ctor(&nvkm_fifo_chan_child_func, oclass, &object->oproxy); in nvkm_fifo_chan_child_new()
150 .client = oclass->client, in nvkm_fifo_chan_child_new()
151 .engine = oclass->engine, in nvkm_fifo_chan_child_new()
169 ret = chan->func->engine_ctor(chan, oclass->engine, in nvkm_fifo_chan_child_new()
176 ret = oclass->base.ctor(&(const struct nvkm_oclass) { in nvkm_fifo_chan_child_new()
177 .base = oclass->base, in nvkm_fifo_chan_child_new()
178 .engn = oclass->engn, in nvkm_fifo_chan_child_new()
[all …]
Dbase.c160 const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_fifo_class_new() argument
163 const struct nvkm_fifo_chan_oclass *sclass = oclass->engn; in nvkm_fifo_class_new()
164 struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); in nvkm_fifo_class_new()
165 return sclass->ctor(fifo, oclass, data, size, pobject); in nvkm_fifo_class_new()
174 nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index, in nvkm_fifo_class_get() argument
177 struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); in nvkm_fifo_class_get()
183 oclass->base = sclass->base; in nvkm_fifo_class_get()
184 oclass->engn = sclass; in nvkm_fifo_class_get()
Ddmanv10.c35 nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in nv10_fifo_dma_new() argument
38 struct nvkm_object *parent = oclass->parent; in nv10_fifo_dma_new()
67 0, 0x800000, 0x10000, oclass, &chan->base); in nv10_fifo_dma_new()
92 .base.oclass = NV10_CHANNEL_DMA,
Ddmanv17.c35 nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in nv17_fifo_dma_new() argument
38 struct nvkm_object *parent = oclass->parent; in nv17_fifo_dma_new()
68 0, 0x800000, 0x10000, oclass, &chan->base); in nv17_fifo_dma_new()
93 .base.oclass = NV17_CHANNEL_DMA,
Dgpfifonv50.c33 nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in nv50_fifo_gpfifo_new() argument
36 struct nvkm_object *parent = oclass->parent; in nv50_fifo_gpfifo_new()
62 oclass, chan); in nv50_fifo_gpfifo_new()
88 .base.oclass = NV50_CHANNEL_GPFIFO,
Ddmanv50.c33 nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in nv50_fifo_dma_new() argument
36 struct nvkm_object *parent = oclass->parent; in nv50_fifo_dma_new()
60 oclass, chan); in nv50_fifo_dma_new()
87 .base.oclass = NV50_CHANNEL_DMA,
Dgpfifog84.c33 g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in g84_fifo_gpfifo_new() argument
36 struct nvkm_object *parent = oclass->parent; in g84_fifo_gpfifo_new()
62 oclass, chan); in g84_fifo_gpfifo_new()
90 .base.oclass = G82_CHANNEL_GPFIFO,
Ddmag84.c33 g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in g84_fifo_dma_new() argument
36 struct nvkm_object *parent = oclass->parent; in g84_fifo_dma_new()
60 oclass, chan); in g84_fifo_dma_new()
89 .base.oclass = G82_CHANNEL_DMA,
Ddmanv40.c180 nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in nv40_fifo_dma_new() argument
183 struct nvkm_object *parent = oclass->parent; in nv40_fifo_dma_new()
213 0, 0xc00000, 0x1000, oclass, &chan->base); in nv40_fifo_dma_new()
239 .base.oclass = NV40_CHANNEL_DMA,
Dgpfifogk104.c204 gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in gk104_fifo_gpfifo_new() argument
212 struct nvkm_object *parent = oclass->parent; in gk104_fifo_gpfifo_new()
238 return nvkm_object_new(oclass, NULL, 0, pobject); in gk104_fifo_gpfifo_new()
263 oclass, &chan->base); in gk104_fifo_gpfifo_new()
319 .base.oclass = KEPLER_CHANNEL_GPFIFO_A,
Ddmanv04.c159 nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in nv04_fifo_dma_new() argument
162 struct nvkm_object *parent = oclass->parent; in nv04_fifo_dma_new()
191 0, 0x800000, 0x10000, oclass, &chan->base); in nv04_fifo_dma_new()
216 .base.oclass = NV03_CHANNEL_DMA,
Dgpfifogf100.c191 gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, in gf100_fifo_gpfifo_new() argument
199 struct nvkm_object *parent = oclass->parent; in gf100_fifo_gpfifo_new()
230 oclass, &chan->base); in gf100_fifo_gpfifo_new()
289 .base.oclass = FERMI_CHANNEL_GPFIFO,
Dgpfifogm204.c30 .base.oclass = MAXWELL_CHANNEL_GPFIFO_A,
Dchang84.c233 const struct nvkm_oclass *oclass, in g84_fifo_chan_ctor() argument
255 0, 0xc00000, 0x2000, oclass, &chan->base); in g84_fifo_chan_ctor()
Dchannv50.c233 const struct nvkm_oclass *oclass, in nv50_fifo_chan_ctor() argument
245 0, 0xc00000, 0x2000, oclass, &chan->base); in nv50_fifo_chan_ctor()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/sw/
Dbase.c50 nvkm_sw_oclass_new(const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_sw_oclass_new() argument
53 struct nvkm_sw_chan *chan = nvkm_sw_chan(oclass->parent); in nvkm_sw_oclass_new()
54 const struct nvkm_sw_chan_sclass *sclass = oclass->engn; in nvkm_sw_oclass_new()
55 return sclass->ctor(chan, oclass, data, size, pobject); in nvkm_sw_oclass_new()
59 nvkm_sw_oclass_get(struct nvkm_oclass *oclass, int index) in nvkm_sw_oclass_get() argument
61 struct nvkm_sw *sw = nvkm_sw(oclass->engine); in nvkm_sw_oclass_get()
66 oclass->engn = &sw->func->sclass[index]; in nvkm_sw_oclass_get()
67 oclass->base = sw->func->sclass[index].base; in nvkm_sw_oclass_get()
68 oclass->base.ctor = nvkm_sw_oclass_new; in nvkm_sw_oclass_get()
78 const struct nvkm_oclass *oclass, in nvkm_sw_cclass_get() argument
[all …]
Dnvsw.c61 const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_nvsw_new_() argument
70 nvkm_object_ctor(&nvkm_nvsw_, oclass, &nvsw->object); in nvkm_nvsw_new_()
81 nvkm_nvsw_new(struct nvkm_sw_chan *chan, const struct nvkm_oclass *oclass, in nvkm_nvsw_new() argument
84 return nvkm_nvsw_new_(&nvkm_nvsw, chan, oclass, data, size, pobject); in nvkm_nvsw_new()
Dnv04.c76 nv04_nvsw_new(struct nvkm_sw_chan *chan, const struct nvkm_oclass *oclass, in nv04_nvsw_new() argument
79 return nvkm_nvsw_new_(&nv04_nvsw, chan, oclass, data, size, pobject); in nv04_nvsw_new()
109 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv04_sw_chan_new() argument
118 return nvkm_sw_chan_ctor(&nv04_sw_chan, sw, fifo, oclass, &chan->base); in nv04_sw_chan_new()
Dnv10.c40 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv10_sw_chan_new() argument
48 return nvkm_sw_chan_ctor(&nv10_sw_chan, sw, fifo, oclass, chan); in nv10_sw_chan_new()
Dchan.c97 struct nvkm_fifo_chan *fifo, const struct nvkm_oclass *oclass, in nvkm_sw_chan_ctor() argument
102 nvkm_object_ctor(&nvkm_sw_chan, oclass, &chan->object); in nvkm_sw_chan_ctor()
Dgf100.c106 const struct nvkm_oclass *oclass, in gf100_sw_chan_new() argument
117 ret = nvkm_sw_chan_ctor(&gf100_sw_chan, sw, fifoch, oclass, in gf100_sw_chan_new()
Dnv50.c101 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv50_sw_chan_new() argument
111 ret = nvkm_sw_chan_ctor(&nv50_sw_chan, sw, fifoch, oclass, &chan->base); in nv50_sw_chan_new()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/core/
Dioctl.c54 struct nvkm_oclass oclass; in nvkm_ioctl_sclass() local
61 if (size != args->v0.count * sizeof(args->v0.oclass[0])) in nvkm_ioctl_sclass()
65 object->func->sclass(object, i, &oclass) >= 0) { in nvkm_ioctl_sclass()
67 args->v0.oclass[i].oclass = oclass.base.oclass; in nvkm_ioctl_sclass()
68 args->v0.oclass[i].minver = oclass.base.minver; in nvkm_ioctl_sclass()
69 args->v0.oclass[i].maxver = oclass.base.maxver; in nvkm_ioctl_sclass()
88 struct nvkm_oclass oclass; in nvkm_ioctl_new() local
95 args->v0.version, args->v0.handle, args->v0.oclass, in nvkm_ioctl_new()
106 memset(&oclass, 0x00, sizeof(oclass)); in nvkm_ioctl_new()
107 oclass.client = client; in nvkm_ioctl_new()
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Dobject.c226 const struct nvkm_oclass *oclass, struct nvkm_object *object) in nvkm_object_ctor() argument
229 object->client = oclass->client; in nvkm_object_ctor()
230 object->engine = nvkm_engine_ref(oclass->engine); in nvkm_object_ctor()
231 object->oclass = oclass->base.oclass; in nvkm_object_ctor()
232 object->handle = oclass->handle; in nvkm_object_ctor()
236 WARN_ON(oclass->engine && !object->engine); in nvkm_object_ctor()
241 const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_object_new_() argument
247 nvkm_object_ctor(func, oclass, *pobject); in nvkm_object_new_()
258 nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_object_new() argument
262 oclass->base.func ? oclass->base.func : &nvkm_object_func; in nvkm_object_new()
[all …]
Doproxy.c91 struct nvkm_oclass *oclass) in nvkm_oproxy_sclass() argument
94 oclass->parent = oproxy->object; in nvkm_oproxy_sclass()
97 return oproxy->object->func->sclass(oproxy->object, index, oclass); in nvkm_oproxy_sclass()
186 const struct nvkm_oclass *oclass, struct nvkm_oproxy *oproxy) in nvkm_oproxy_ctor() argument
188 nvkm_object_ctor(&nvkm_oproxy_func, oclass, &oproxy->base); in nvkm_oproxy_ctor()
194 const struct nvkm_oclass *oclass, struct nvkm_oproxy **poproxy) in nvkm_oproxy_new_() argument
198 nvkm_oproxy_ctor(func, oclass, *poproxy); in nvkm_oproxy_new_()
Dclient.c179 nvkm_client_child_new(const struct nvkm_oclass *oclass, in nvkm_client_child_new() argument
182 return oclass->base.ctor(oclass, data, size, pobject); in nvkm_client_child_new()
187 struct nvkm_oclass *oclass) in nvkm_client_child_get() argument
197 oclass->ctor = nvkm_client_child_new; in nvkm_client_child_get()
198 oclass->base = *sclass; in nvkm_client_child_get()
294 struct nvkm_oclass oclass = {}; in nvkm_client_new() local
299 oclass.client = client; in nvkm_client_new()
301 nvkm_object_ctor(&nvkm_client_object_func, &oclass, &client->object); in nvkm_client_new()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/dma/
Dbase.c51 const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_dma_oclass_new() argument
54 struct nvkm_dma *dma = nvkm_dma(oclass->engine); in nvkm_dma_oclass_new()
56 struct nvkm_client *client = oclass->client; in nvkm_dma_oclass_new()
61 ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); in nvkm_dma_oclass_new()
67 dmaobj->handle = oclass->object; in nvkm_dma_oclass_new()
92 nvkm_dma_oclass_fifo_new(const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_dma_oclass_fifo_new() argument
95 return nvkm_dma_oclass_new(oclass->engine->subdev.device, in nvkm_dma_oclass_fifo_new()
96 oclass, data, size, pobject); in nvkm_dma_oclass_fifo_new()
112 const struct nvkm_sclass *oclass = &nvkm_dma_sclass[index]; in nvkm_dma_oclass_base_get() local
113 sclass->base = oclass[0]; in nvkm_dma_oclass_base_get()
[all …]
Dusergf100.c70 gf100_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, in gf100_dmaobj_new() argument
76 struct nvkm_object *parent = oclass->parent; in gf100_dmaobj_new()
85 ret = nvkm_dmaobj_ctor(&gf100_dmaobj_func, dma, oclass, in gf100_dmaobj_new()
116 dmaobj->flags0 |= (kind << 22) | (user << 20) | oclass->base.oclass; in gf100_dmaobj_new()
Dusernv50.c70 nv50_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, in nv50_dmaobj_new() argument
76 struct nvkm_object *parent = oclass->parent; in nv50_dmaobj_new()
85 ret = nvkm_dmaobj_ctor(&nv50_dmaobj_func, dma, oclass, in nv50_dmaobj_new()
121 oclass->base.oclass; in nv50_dmaobj_new()
Dusernv04.c81 nv04_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, in nv04_dmaobj_new() argument
92 ret = nvkm_dmaobj_ctor(&nv04_dmaobj_func, dma, oclass, in nv04_dmaobj_new()
104 dmaobj->flags0 = oclass->base.oclass; in nv04_dmaobj_new()
Duser.c59 const struct nvkm_oclass *oclass, void **pdata, u32 *psize, in nvkm_dmaobj_ctor() argument
66 struct nvkm_client *client = oclass->client; in nvkm_dmaobj_ctor()
67 struct nvkm_object *parent = oclass->parent; in nvkm_dmaobj_ctor()
74 nvkm_object_ctor(&nvkm_dmaobj_func, oclass, &dmaobj->object); in nvkm_dmaobj_ctor()
Dusergf119.c68 gf119_dmaobj_new(struct nvkm_dma *dma, const struct nvkm_oclass *oclass, in gf119_dmaobj_new() argument
74 struct nvkm_object *parent = oclass->parent; in gf119_dmaobj_new()
83 ret = nvkm_dmaobj_ctor(&gf119_dmaobj_func, dma, oclass, in gf119_dmaobj_new()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dbase.c53 nvkm_gr_oclass_get(struct nvkm_oclass *oclass, int index) in nvkm_gr_oclass_get() argument
55 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_oclass_get()
59 int ret = gr->func->object_get(gr, index, &oclass->base); in nvkm_gr_oclass_get()
60 if (oclass->base.oclass) in nvkm_gr_oclass_get()
65 while (gr->func->sclass[c].oclass) { in nvkm_gr_oclass_get()
67 oclass->base = gr->func->sclass[index]; in nvkm_gr_oclass_get()
77 const struct nvkm_oclass *oclass, in nvkm_gr_cclass_new() argument
80 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_cclass_new()
82 return gr->func->chan_new(gr, chan, oclass, pobject); in nvkm_gr_cclass_new()
Dnv2a.c21 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv2a_gr_chan_new() argument
29 nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object); in nv2a_gr_chan_new()
Dnv34.c21 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv34_gr_chan_new() argument
29 nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); in nv34_gr_chan_new()
Dnv35.c21 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv35_gr_chan_new() argument
29 nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); in nv35_gr_chan_new()
Dnv25.c21 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv25_gr_chan_new() argument
29 nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); in nv25_gr_chan_new()
Dnv30.c22 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv30_gr_chan_new() argument
30 nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object); in nv30_gr_chan_new()
Dnv40.c51 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv40_gr_object_bind()
149 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv40_gr_chan_new() argument
157 nvkm_object_ctor(&nv40_gr_chan, oclass, &chan->object); in nv40_gr_chan_new()
Dnv50.c48 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
88 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv50_gr_chan_new() argument
95 nvkm_object_ctor(&nv50_gr_chan, oclass, &chan->object); in nv50_gr_chan_new()
Dnv20.c75 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv20_gr_chan_new() argument
83 nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object); in nv20_gr_chan_new()
Dnv04.c1050 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv04_gr_object_bind()
1185 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv04_gr_chan_new() argument
1193 nvkm_object_ctor(&nv04_gr_chan, oclass, &chan->object); in nv04_gr_chan_new()
Dnv10.c1003 const struct nvkm_oclass *oclass, struct nvkm_object **pobject) in nv10_gr_chan_new() argument
1012 nvkm_object_ctor(&nv10_gr_chan, oclass, &chan->object); in nv10_gr_chan_new()
Dgf100.c265 while (gr->func->sclass[c].oclass) { in gf100_gr_object_get()
344 const struct nvkm_oclass *oclass, in gf100_gr_chan_new() argument
356 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); in gf100_gr_chan_new()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Ddmacnv50.c55 const struct nvkm_oclass *oclass, in nv50_disp_dmac_child_new_() argument
61 const struct nvkm_device_oclass *sclass = oclass->priv; in nv50_disp_dmac_child_new_()
67 nvkm_oproxy_ctor(&nv50_disp_dmac_child_func_, oclass, &object->oproxy); in nv50_disp_dmac_child_new_()
71 ret = sclass->ctor(device, oclass, data, size, &object->oproxy.object); in nv50_disp_dmac_child_new_()
76 oclass->handle); in nv50_disp_dmac_child_new_()
90 const struct nvkm_device_oclass *oclass = NULL; in nv50_disp_dmac_child_get_() local
94 sclass->engine->func->base.sclass(sclass, index, &oclass); in nv50_disp_dmac_child_get_()
95 if (oclass) { in nv50_disp_dmac_child_get_()
96 sclass->priv = oclass; in nv50_disp_dmac_child_get_()
137 const struct nvkm_oclass *oclass, in nv50_disp_dmac_new_() argument
[all …]
Doimmnv50.c36 const struct nvkm_oclass *oclass, void *data, u32 size, in nv50_disp_oimm_new() argument
42 struct nvkm_object *parent = oclass->parent; in nv50_disp_oimm_new()
57 head, oclass, pobject); in nv50_disp_oimm_new()
62 .base.oclass = NV50_DISP_OVERLAY,
Dcursnv50.c36 const struct nvkm_oclass *oclass, void *data, u32 size, in nv50_disp_curs_new() argument
42 struct nvkm_object *parent = oclass->parent; in nv50_disp_curs_new()
57 head, oclass, pobject); in nv50_disp_curs_new()
62 .base.oclass = NV50_DISP_CURSOR,
Drootnv50.c192 nv50_disp_root_dmac_new_(const struct nvkm_oclass *oclass, in nv50_disp_root_dmac_new_() argument
195 const struct nv50_disp_dmac_oclass *sclass = oclass->priv; in nv50_disp_root_dmac_new_()
196 struct nv50_disp_root *root = nv50_disp_root(oclass->parent); in nv50_disp_root_dmac_new_()
198 oclass, data, size, pobject); in nv50_disp_root_dmac_new_()
202 nv50_disp_root_pioc_new_(const struct nvkm_oclass *oclass, in nv50_disp_root_pioc_new_() argument
205 const struct nv50_disp_pioc_oclass *sclass = oclass->priv; in nv50_disp_root_pioc_new_()
206 struct nv50_disp_root *root = nv50_disp_root(oclass->parent); in nv50_disp_root_pioc_new_()
208 oclass, data, size, pobject); in nv50_disp_root_pioc_new_()
272 struct nvkm_disp *base, const struct nvkm_oclass *oclass, in nv50_disp_root_new_() argument
284 nvkm_object_ctor(&nv50_disp_root_, oclass, &root->object); in nv50_disp_root_new_()
[all …]
Dchannv50.c205 nv50_disp_chan_child_new(const struct nvkm_oclass *oclass, in nv50_disp_chan_child_new() argument
208 struct nv50_disp_chan *chan = nv50_disp_chan(oclass->parent); in nv50_disp_chan_child_new()
209 return chan->func->child_new(chan, oclass, data, size, pobject); in nv50_disp_chan_child_new()
214 struct nvkm_oclass *oclass) in nv50_disp_chan_child_get() argument
218 int ret = chan->func->child_get(chan, index, oclass); in nv50_disp_chan_child_get()
220 oclass->ctor = nv50_disp_chan_child_new; in nv50_disp_chan_child_get()
267 const struct nvkm_oclass *oclass, in nv50_disp_chan_ctor() argument
272 nvkm_object_ctor(&nv50_disp_chan, oclass, &chan->object); in nv50_disp_chan_ctor()
291 const struct nvkm_oclass *oclass, in nv50_disp_chan_new_() argument
300 return nv50_disp_chan_ctor(func, mthd, root, chid, head, oclass, chan); in nv50_disp_chan_new_()
Dovlynv50.c36 const struct nvkm_oclass *oclass, void *data, u32 size, in nv50_disp_ovly_new() argument
42 struct nvkm_object *parent = oclass->parent; in nv50_disp_ovly_new()
60 head, push, oclass, pobject); in nv50_disp_ovly_new()
104 .base.oclass = NV50_DISP_OVERLAY_CHANNEL_DMA,
Dbasenv50.c36 const struct nvkm_oclass *oclass, void *data, u32 size, in nv50_disp_base_new() argument
42 struct nvkm_object *parent = oclass->parent; in nv50_disp_base_new()
60 head, push, oclass, pobject); in nv50_disp_base_new()
116 .base.oclass = NV50_DISP_BASE_CHANNEL_DMA,
Drootg94.c45 g94_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in g94_disp_root_new() argument
48 return nv50_disp_root_new_(&g94_disp_root, disp, oclass, in g94_disp_root_new()
54 .base.oclass = GT206_DISP,
Drootgt200.c45 gt200_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gt200_disp_root_new() argument
48 return nv50_disp_root_new_(&gt200_disp_root, disp, oclass, in gt200_disp_root_new()
54 .base.oclass = GT200_DISP,
Drootgm107.c45 gm107_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gm107_disp_root_new() argument
48 return nv50_disp_root_new_(&gm107_disp_root, disp, oclass, in gm107_disp_root_new()
54 .base.oclass = GM107_DISP,
Drootgm204.c45 gm204_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gm204_disp_root_new() argument
48 return nv50_disp_root_new_(&gm204_disp_root, disp, oclass, in gm204_disp_root_new()
54 .base.oclass = GM204_DISP,
Drootgt215.c45 gt215_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gt215_disp_root_new() argument
48 return nv50_disp_root_new_(&gt215_disp_root, disp, oclass, in gt215_disp_root_new()
54 .base.oclass = GT214_DISP,
Drootgk104.c45 gk104_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gk104_disp_root_new() argument
48 return nv50_disp_root_new_(&gk104_disp_root, disp, oclass, in gk104_disp_root_new()
54 .base.oclass = GK104_DISP,
Drootgk110.c45 gk110_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gk110_disp_root_new() argument
48 return nv50_disp_root_new_(&gk110_disp_root, disp, oclass, in gk110_disp_root_new()
54 .base.oclass = GK110_DISP,
Drootg84.c45 g84_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in g84_disp_root_new() argument
48 return nv50_disp_root_new_(&g84_disp_root, disp, oclass, in g84_disp_root_new()
54 .base.oclass = G82_DISP,
Dcorenv50.c37 const struct nvkm_oclass *oclass, void *data, u32 size, in nv50_disp_core_new() argument
43 struct nvkm_object *parent = oclass->parent; in nv50_disp_core_new()
57 push, oclass, pobject); in nv50_disp_core_new()
235 .base.oclass = NV50_DISP_CORE_CHANNEL_DMA,
Dbase.c157 const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_disp_class_new() argument
160 const struct nvkm_disp_oclass *sclass = oclass->engn; in nvkm_disp_class_new()
161 struct nvkm_disp *disp = nvkm_disp(oclass->engine); in nvkm_disp_class_new()
165 ret = nvkm_oproxy_new_(&nvkm_disp_class, oclass, &oproxy); in nvkm_disp_class_new()
178 return sclass->ctor(disp, oclass, data, size, &oproxy->object); in nvkm_disp_class_new()
187 nvkm_disp_class_get(struct nvkm_oclass *oclass, int index, in nvkm_disp_class_get() argument
190 struct nvkm_disp *disp = nvkm_disp(oclass->engine); in nvkm_disp_class_get()
193 oclass->base = root->base; in nvkm_disp_class_get()
194 oclass->engn = root; in nvkm_disp_class_get()
Ddmacnv50.h46 const struct nvkm_oclass *oclass, void *data, u32 size,
51 const struct nvkm_oclass *oclass, void *data, u32 size,
56 const struct nvkm_oclass *oclass, void *data, u32 size,
Drootnv04.c119 nv04_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in nv04_disp_root_new() argument
129 nvkm_object_ctor(&nv04_disp_root, oclass, &root->object); in nv04_disp_root_new()
135 .base.oclass = NV04_DISP,
Drootgf119.c158 gf119_disp_root_new(struct nvkm_disp *disp, const struct nvkm_oclass *oclass, in gf119_disp_root_new() argument
161 return nv50_disp_root_new_(&gf119_disp_root, disp, oclass, in gf119_disp_root_new()
167 .base.oclass = GF110_DISP,
Dcursgk104.c31 .base.oclass = GK104_DISP_CURSOR,
Doimmgk104.c31 .base.oclass = GK104_DISP_OVERLAY,
Dcursg84.c31 .base.oclass = G82_DISP_CURSOR,
Doimmgt215.c31 .base.oclass = GT214_DISP_OVERLAY,
Doimmgf119.c31 .base.oclass = GF110_DISP_OVERLAY,
Dcursgf119.c31 .base.oclass = GF110_DISP_CURSOR,
Doimmg84.c31 .base.oclass = G82_DISP_OVERLAY,
Dcursgt215.c31 .base.oclass = GT214_DISP_CURSOR,
Dcoregt200.c31 .base.oclass = GT200_DISP_CORE_CHANNEL_DMA,
Dbasegk104.c31 .base.oclass = GK104_DISP_BASE_CHANNEL_DMA,
Dbasegt215.c31 .base.oclass = GT214_DISP_BASE_CHANNEL_DMA,
Dbasegk110.c31 .base.oclass = GK110_DISP_BASE_CHANNEL_DMA,
Dcoregm204.c31 .base.oclass = GM204_DISP_CORE_CHANNEL_DMA,
Dcoregm107.c31 .base.oclass = GM107_DISP_CORE_CHANNEL_DMA,
Dcoregt215.c31 .base.oclass = GT214_DISP_CORE_CHANNEL_DMA,
Dovlygt215.c31 .base.oclass = GT214_DISP_OVERLAY_CHANNEL_DMA,
Dcoregk110.c31 .base.oclass = GK110_DISP_CORE_CHANNEL_DMA,
Dbasegt200.c31 .base.oclass = GT200_DISP_BASE_CHANNEL_DMA,
Dovlygk104.c96 .base.oclass = GK104_DISP_OVERLAY_CONTROL_DMA,
Dovlygf119.c94 .base.oclass = GF110_DISP_OVERLAY_CONTROL_DMA,
Dovlyg84.c70 .base.oclass = G82_DISP_OVERLAY_CHANNEL_DMA,
Dovlygt200.c73 .base.oclass = GT200_DISP_OVERLAY_CHANNEL_DMA,
Dbaseg84.c73 .base.oclass = G82_DISP_BASE_CHANNEL_DMA,
Dcoregk104.c125 .base.oclass = GK104_DISP_CORE_CHANNEL_DMA,
Dcoreg94.c56 .base.oclass = GT206_DISP_CORE_CHANNEL_DMA,
Dbasegf119.c107 .base.oclass = GF110_DISP_BASE_CHANNEL_DMA,
Dcoreg84.c110 .base.oclass = G82_DISP_CORE_CHANNEL_DMA,
Dcoregf119.c237 .base.oclass = GF110_DISP_CORE_CHANNEL_DMA,
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/device/
Duser.c255 nvkm_udevice_child_new(const struct nvkm_oclass *oclass, in nvkm_udevice_child_new() argument
258 struct nvkm_udevice *udev = nvkm_udevice(oclass->parent); in nvkm_udevice_child_new()
259 const struct nvkm_device_oclass *sclass = oclass->priv; in nvkm_udevice_child_new()
260 return sclass->ctor(udev->device, oclass, data, size, pobject); in nvkm_udevice_child_new()
265 struct nvkm_oclass *oclass) in nvkm_udevice_child_get() argument
281 oclass->engine = engine; in nvkm_udevice_child_get()
283 index -= engine->func->base.sclass(oclass, index, &sclass); in nvkm_udevice_child_get()
292 oclass->base = sclass->base; in nvkm_udevice_child_get()
295 oclass->ctor = nvkm_udevice_child_new; in nvkm_udevice_child_get()
296 oclass->priv = sclass; in nvkm_udevice_child_get()
[all …]
Dctrl.c191 nvkm_control_new(struct nvkm_device *device, const struct nvkm_oclass *oclass, in nvkm_control_new() argument
201 nvkm_object_ctor(&nvkm_control, oclass, &ctrl->object); in nvkm_control_new()
207 .base.oclass = NVIF_IOCTL_NEW_V0_CONTROL,
/linux-4.4.14/drivers/gpu/drm/nouveau/nvif/
Dobject.c69 size = sizeof(*args) + cnt * sizeof(args->sclass.oclass[0]); in nvif_object_sclass_get()
89 (*psclass)[i].oclass = args->sclass.oclass[i].oclass; in nvif_object_sclass_get()
90 (*psclass)[i].minver = args->sclass.oclass[i].minver; in nvif_object_sclass_get()
91 (*psclass)[i].maxver = args->sclass.oclass[i].maxver; in nvif_object_sclass_get()
232 nvif_object_init(struct nvif_object *parent, u32 handle, s32 oclass, in nvif_object_init() argument
243 object->oclass = oclass; in nvif_object_init()
260 args->new.oclass = oclass; in nvif_object_init()
Ddevice.c44 nvif_device_init(struct nvif_object *parent, u32 handle, s32 oclass, in nvif_device_init() argument
47 int ret = nvif_object_init(parent, handle, oclass, data, size, in nvif_device_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/
Dnouveau_abi16.c414 s32 oclass = 0; in nouveau_abi16_ioctl_grobj_alloc() local
434 for (i = 0; !oclass && i < ret; i++) { in nouveau_abi16_ioctl_grobj_alloc()
435 switch (sclass[i].oclass) { in nouveau_abi16_ioctl_grobj_alloc()
440 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
450 if ((sclass[i].oclass & 0x00ff) == 0x00b1) { in nouveau_abi16_ioctl_grobj_alloc()
451 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
459 if ((sclass[i].oclass & 0x00ff) == 0x00b2) { in nouveau_abi16_ioctl_grobj_alloc()
460 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
468 if ((sclass[i].oclass & 0x00ff) == 0x00b3) { in nouveau_abi16_ioctl_grobj_alloc()
469 oclass = sclass[i].oclass; in nouveau_abi16_ioctl_grobj_alloc()
[all …]
Dnouveau_chan.c195 const u16 *oclass = oclasses; in nouveau_channel_ind() local
213 if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { in nouveau_channel_ind()
221 if (oclass[0] >= FERMI_CHANNEL_GPFIFO) { in nouveau_channel_ind()
236 ret = nvif_object_init(&device->object, 0, *oclass++, in nouveau_channel_ind()
239 if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) in nouveau_channel_ind()
242 if (chan->user.oclass >= FERMI_CHANNEL_GPFIFO) in nouveau_channel_ind()
248 } while (*oclass); in nouveau_channel_ind()
263 const u16 *oclass = oclasses; in nouveau_channel_dma() local
280 ret = nvif_object_init(&device->object, 0, *oclass++, in nouveau_channel_dma()
286 } while (ret && *oclass); in nouveau_channel_dma()
[all …]
Dnv50_display.c68 const s32 *oclass, u8 head, void *data, u32 size, in nv50_chan_create() argument
80 while (oclass[0]) { in nv50_chan_create()
82 if (sclass[i].oclass == oclass[0]) { in nv50_chan_create()
83 ret = nvif_object_init(disp, 0, oclass[0], in nv50_chan_create()
91 oclass++; in nv50_chan_create()
120 const s32 *oclass, u8 head, void *data, u32 size, in nv50_pioc_create() argument
123 return nv50_chan_create(device, disp, oclass, head, data, size, in nv50_pioc_create()
142 static const s32 oclass[] = { in nv50_curs_create() local
151 return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args), in nv50_curs_create()
170 static const s32 oclass[] = { in nv50_oimm_create() local
[all …]
Dnouveau_display.c417 if (disp->disp.oclass < NV50_DISP) in nouveau_display_create_properties()
420 if (disp->disp.oclass < GF110_DISP) in nouveau_display_create_properties()
496 static const u16 oclass[] = { in nouveau_display_create() local
511 for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { in nouveau_display_create()
513 oclass[i], NULL, 0, &disp->disp); in nouveau_display_create()
518 if (disp->disp.oclass < NV50_DISP) in nouveau_display_create()
Dnouveau_connector.c476 if (disp->disp.oclass < NV50_DISP) in nouveau_connector_set_property()
1209 if (disp->disp.oclass < NV50_DISP) { in nouveau_connector_create()
1227 if (disp->disp.oclass < NV50_DISP) in nouveau_connector_create()
Dnouveau_bo.c1101 s32 oclass; in nouveau_bo_move_init() member
1135 mthd->oclass | (mthd->engine << 16), in nouveau_bo_move_init()
1136 mthd->oclass, NULL, 0, in nouveau_bo_move_init()
Dnouveau_drm.c176 switch (sclass[i].oclass) { in nouveau_accel_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Dbase.c365 const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_perfdom_new_() argument
372 struct nvkm_object *parent = oclass->parent; in nvkm_perfdom_new_()
416 nvkm_object_ctor(&nvkm_perfdom, oclass, &dom->object); in nvkm_perfdom_new_()
603 nvkm_perfmon_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, in nvkm_perfmon_child_new() argument
606 struct nvkm_perfmon *perfmon = nvkm_perfmon(oclass->parent); in nvkm_perfmon_child_new()
607 return nvkm_perfdom_new_(perfmon, oclass, data, size, pobject); in nvkm_perfmon_child_new()
612 struct nvkm_oclass *oclass) in nvkm_perfmon_child_get() argument
615 oclass->base.oclass = NVIF_IOCTL_NEW_V0_PERFDOM; in nvkm_perfmon_child_get()
616 oclass->base.minver = 0; in nvkm_perfmon_child_get()
617 oclass->base.maxver = 0; in nvkm_perfmon_child_get()
[all …]
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvif/
Dioctl.h44 __s32 oclass; member
47 } oclass[]; member
66 __s32 oclass; member
Dobject.h7 s32 oclass; member
15 s32 oclass; member
23 int nvif_object_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32,
Ddevice.h12 int nvif_device_init(struct nvif_object *, u32 handle, s32 oclass, void *, u32,
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c28 nvkm_xtensa_oclass_get(struct nvkm_oclass *oclass, int index) in nvkm_xtensa_oclass_get() argument
30 struct nvkm_xtensa *xtensa = nvkm_xtensa(oclass->engine); in nvkm_xtensa_oclass_get()
33 while (xtensa->func->sclass[c].oclass) { in nvkm_xtensa_oclass_get()
35 oclass->base = xtensa->func->sclass[index]; in nvkm_xtensa_oclass_get()
Dfalcon.c29 nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index) in nvkm_falcon_oclass_get() argument
31 struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); in nvkm_falcon_oclass_get()
34 while (falcon->func->sclass[c].oclass) { in nvkm_falcon_oclass_get()
36 oclass->base = falcon->func->sclass[index]; in nvkm_falcon_oclass_get()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv31.c46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv31_mpeg_object_bind()
85 const struct nvkm_oclass *oclass, in nv31_mpeg_chan_new() argument
88 struct nv31_mpeg *mpeg = nv31_mpeg(oclass->engine); in nv31_mpeg_chan_new()
95 nvkm_object_ctor(&nv31_mpeg_chan, oclass, &chan->object); in nv31_mpeg_chan_new()
Dnv44.c104 const struct nvkm_oclass *oclass, in nv44_mpeg_chan_new() argument
107 struct nv44_mpeg *mpeg = nv44_mpeg(oclass->engine); in nv44_mpeg_chan_new()
113 nvkm_object_ctor(&nv44_mpeg_chan, oclass, &chan->object); in nv44_mpeg_chan_new()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/
Dobject.h13 s32 oclass; member
68 s32 oclass; member
Dclient.h44 _object->handle, _object->oclass, ##a); \
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c41 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in g84_cipher_oclass_bind()