/linux-4.4.14/arch/arm/mach-davinci/ |
H A D | mux.h | 23 .mux_reg = PINMUX(muxreg), \ 34 .mux_reg = INTMUX, \ 45 .mux_reg = EVTMUX, \
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H A D | mux.c | 70 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); davinci_cfg_reg() 82 __raw_writel(reg, pinmux_base + cfg->mux_reg); davinci_cfg_reg() 96 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); davinci_cfg_reg()
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/linux-4.4.14/arch/arm/mach-omap1/include/mach/ |
H A D | mux.h | 41 .mux_reg = FUNC_MUX_CTRL_##reg, \ 55 .mux_reg = OMAP7XX_IO_CONF_##reg, \ 66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ 78 .mux_reg = OMAP7XX_IO_CONF_##reg, \ 88 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ 94 MUX_REG(mux_reg, mode_offset, mode) \ 107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ 112 MUX_REG_7XX(mux_reg, mode_offset, mode) \ 113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \ 119 const unsigned int mux_reg; member in struct:pin_config
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/linux-4.4.14/drivers/pinctrl/freescale/ |
H A D | pinctrl-imx.c | 209 if (pin_reg->mux_reg == -1) { imx_pmx_set() 217 reg = readl(ipctl->base + pin_reg->mux_reg); imx_pmx_set() 220 writel(reg, ipctl->base + pin_reg->mux_reg); imx_pmx_set() 222 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); imx_pmx_set() 225 pin_reg->mux_reg, pin->mux_mode); imx_pmx_set() 320 if (pin_reg->mux_reg == -1) imx_pmx_gpio_request_enable() 336 reg = readl(ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_request_enable() 339 writel(reg, ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_request_enable() 360 if (pin_reg->mux_reg == -1) imx_pmx_gpio_set_direction() 364 reg = readl(ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_set_direction() 369 writel(reg, ipctl->base + pin_reg->mux_reg); imx_pmx_gpio_set_direction() 546 u32 mux_reg = be32_to_cpu(*list++); imx_pinctrl_parse_groups() local 552 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) imx_pinctrl_parse_groups() 553 mux_reg = -1; imx_pinctrl_parse_groups() 556 conf_reg = mux_reg; imx_pinctrl_parse_groups() 563 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; imx_pinctrl_parse_groups() 567 pin_reg->mux_reg = mux_reg; imx_pinctrl_parse_groups() 718 info->pin_regs[i].mux_reg = -1; imx_pinctrl_probe()
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H A D | pinctrl-imx.h | 66 * @mux_reg: mux register offset 70 s16 mux_reg; member in struct:imx_pin_reg
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/linux-4.4.14/drivers/clk/samsung/ |
H A D | clk-cpu.c | 83 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, wait_until_mux_stable() argument 89 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) wait_until_mux_stable() 93 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) wait_until_mux_stable() 150 unsigned long div0, div1 = 0, mux_reg; exynos_cpuclk_pre_rate_change() local 202 mux_reg = readl(base + E4210_SRC_CPU); exynos_cpuclk_pre_rate_change() 203 writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); exynos_cpuclk_pre_rate_change() 226 unsigned long mux_reg; exynos_cpuclk_post_rate_change() local 241 mux_reg = readl(base + E4210_SRC_CPU); exynos_cpuclk_post_rate_change() 242 writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); exynos_cpuclk_post_rate_change()
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/linux-4.4.14/drivers/pinctrl/ |
H A D | pinctrl-tegra.c | 277 if (WARN_ON(g->mux_reg < 0)) tegra_pinctrl_set_mux() 287 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); tegra_pinctrl_set_mux() 290 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); tegra_pinctrl_set_mux() 323 *reg = g->mux_reg; tegra_pinconf_reg() 329 *reg = g->mux_reg; tegra_pinconf_reg() 335 *reg = g->mux_reg; tegra_pinconf_reg() 341 *reg = g->mux_reg; tegra_pinconf_reg() 347 *reg = g->mux_reg; tegra_pinconf_reg() 354 *reg = g->mux_reg; tegra_pinconf_reg() 365 *reg = g->mux_reg; tegra_pinconf_reg() 406 *reg = g->mux_reg; tegra_pinconf_reg() 679 if (g->mux_reg == -1) tegra_pinctrl_probe()
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H A D | pinctrl-tegra.h | 85 * @mux_reg: Mux register offset. 134 s16 mux_reg; member in struct:tegra_pingroup
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H A D | pinctrl-pistachio.c | 92 int mux_reg; member in struct:pistachio_pin_group 647 .mux_reg = -1, \ 661 .mux_reg = -1, \ 675 .mux_reg = _reg, \ 962 if (pg->mux_reg > 0) { pistachio_pinmux_enable() 973 val = pctl_readl(pctl, pg->mux_reg); pistachio_pinmux_enable() 976 pctl_writel(pctl, val, pg->mux_reg); pistachio_pinmux_enable()
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H A D | pinctrl-tegra124.c | 1736 .mux_reg = PINGROUP_REG(r), \ 1760 .mux_reg = -1, \ 1795 .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
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H A D | pinctrl-tegra20.c | 1988 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \ 2011 .mux_reg = -1, \ 2026 .mux_reg = -1, \
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H A D | pinctrl-tegra210.c | 1299 .mux_reg = PINGROUP_REG(r), \ 1335 .mux_reg = -1, \
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H A D | pinctrl-tegra114.c | 1567 .mux_reg = PINGROUP_REG(r), \ 1591 .mux_reg = -1, \
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H A D | pinctrl-tegra30.c | 2128 .mux_reg = PINGROUP_REG(r), \ 2152 .mux_reg = -1, \
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H A D | pinctrl-palmas.c | 589 dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n", palmas_pinctrl_get_pin_mux()
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/linux-4.4.14/drivers/clk/mediatek/ |
H A D | clk-mtk.h | 72 uint32_t mux_reg; member in struct:mtk_composite 89 .mux_reg = _reg, \ 103 .mux_reg = _reg, \
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H A D | clk-mtk.c | 157 mux->reg = base + mc->mux_reg; mtk_clk_register_composite()
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/linux-4.4.14/arch/arm/mach-omap1/ |
H A D | mux.c | 355 if (cfg->mux_reg) { omap1_cfg_reg() 359 reg_orig = omap_readl(cfg->mux_reg); omap1_cfg_reg() 372 omap_writel(reg, cfg->mux_reg); omap1_cfg_reg() 431 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); omap1_cfg_reg()
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/linux-4.4.14/arch/arm/mach-davinci/include/mach/ |
H A D | mux.h | 25 const unsigned char mux_reg; member in struct:mux_config
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/linux-4.4.14/drivers/pinctrl/sirf/ |
H A D | pinctrl-atlas7.c | 173 * @mux_reg: The mux register offset. 187 u32 mux_reg; member in struct:atlas7_pad_config 202 .mux_reg = mr, \ 5069 pmx->regs[bank] + CLR_REG(conf->mux_reg)); __atlas7_pmx_pin_enable() 5072 regv = readl(pmx->regs[bank] + conf->mux_reg); __atlas7_pmx_pin_enable() 5075 pmx->regs[bank] + conf->mux_reg); __atlas7_pmx_pin_enable() 5077 regv = readl(pmx->regs[bank] + conf->mux_reg); __atlas7_pmx_pin_enable() 5079 bank, conf->mux_reg, regv); __atlas7_pmx_pin_enable() 5457 regv = readl(pmx->regs[bank] + conf->mux_reg); atlas7_pinmux_suspend_noirq()
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/linux-4.4.14/arch/arm/boot/dts/ |
H A D | imx25-pinfunc.h | 17 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx51-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx6ul-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | vf610-pinfunc.h | 15 * <mux_reg input_reg mux_mode input_val>
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H A D | imx35-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx50-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx6q-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx53-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx6dl-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx6sl-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx7d-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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H A D | imx6sx-pinfunc.h | 15 * <mux_reg conf_reg input_reg mux_mode input_val>
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