| /linux-4.4.14/arch/arm/mach-omap1/include/mach/ |
| D | mux.h | 41 .mux_reg = FUNC_MUX_CTRL_##reg, \
55 .mux_reg = OMAP7XX_IO_CONF_##reg, \
66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
78 .mux_reg = OMAP7XX_IO_CONF_##reg, \
88 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ argument
94 MUX_REG(mux_reg, mode_offset, mode) \
107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ argument
112 MUX_REG_7XX(mux_reg, mode_offset, mode) \
113 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
119 const unsigned int mux_reg; member
|
| /linux-4.4.14/drivers/clk/samsung/ |
| D | clk-cpu.c | 83 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, in wait_until_mux_stable() argument
89 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
93 if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value) in wait_until_mux_stable()
150 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
202 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
203 writel(mux_reg | (1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_pre_rate_change()
226 unsigned long mux_reg; in exynos_cpuclk_post_rate_change() local
241 mux_reg = readl(base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
242 writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); in exynos_cpuclk_post_rate_change()
|
| /linux-4.4.14/drivers/pinctrl/freescale/ |
| D | pinctrl-imx.c | 209 if (pin_reg->mux_reg == -1) { in imx_pmx_set()
217 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
220 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
222 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set()
225 pin_reg->mux_reg, pin->mux_mode); in imx_pmx_set()
320 if (pin_reg->mux_reg == -1) in imx_pmx_gpio_request_enable()
336 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_gpio_request_enable()
339 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_gpio_request_enable()
360 if (pin_reg->mux_reg == -1) in imx_pmx_gpio_set_direction()
364 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_gpio_set_direction()
[all …]
|
| D | pinctrl-imx.h | 70 s16 mux_reg; member
|
| /linux-4.4.14/arch/arm/mach-davinci/ |
| D | mux.h | 23 .mux_reg = PINMUX(muxreg), \
34 .mux_reg = INTMUX, \
45 .mux_reg = EVTMUX, \
|
| D | mux.c | 70 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
82 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
96 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in davinci_cfg_reg()
|
| /linux-4.4.14/drivers/pinctrl/ |
| D | pinctrl-tegra.c | 277 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
287 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
290 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
323 *reg = g->mux_reg; in tegra_pinconf_reg()
329 *reg = g->mux_reg; in tegra_pinconf_reg()
335 *reg = g->mux_reg; in tegra_pinconf_reg()
341 *reg = g->mux_reg; in tegra_pinconf_reg()
347 *reg = g->mux_reg; in tegra_pinconf_reg()
354 *reg = g->mux_reg; in tegra_pinconf_reg()
365 *reg = g->mux_reg; in tegra_pinconf_reg()
[all …]
|
| D | pinctrl-tegra.h | 134 s16 mux_reg; member
|
| D | pinctrl-pistachio.c | 92 int mux_reg; member
647 .mux_reg = -1, \
661 .mux_reg = -1, \
675 .mux_reg = _reg, \
962 if (pg->mux_reg > 0) { in pistachio_pinmux_enable()
973 val = pctl_readl(pctl, pg->mux_reg); in pistachio_pinmux_enable()
976 pctl_writel(pctl, val, pg->mux_reg); in pistachio_pinmux_enable()
|
| D | pinctrl-tegra20.c | 1988 .mux_reg = ((mux_r) - PIN_MUX_CTL_REG_A), \
2011 .mux_reg = -1, \
2026 .mux_reg = -1, \
|
| D | pinctrl-tegra124.c | 1736 .mux_reg = PINGROUP_REG(r), \
1760 .mux_reg = -1, \
1795 .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
|
| D | pinctrl-tegra210.c | 1299 .mux_reg = PINGROUP_REG(r), \
1335 .mux_reg = -1, \
|
| D | pinctrl-tegra114.c | 1567 .mux_reg = PINGROUP_REG(r), \
1591 .mux_reg = -1, \
|
| D | pinctrl-tegra30.c | 2128 .mux_reg = PINGROUP_REG(r), \
2152 .mux_reg = -1, \
|
| /linux-4.4.14/drivers/clk/mediatek/ |
| D | clk-mtk.h | 72 uint32_t mux_reg; member
89 .mux_reg = _reg, \
103 .mux_reg = _reg, \
|
| D | clk-mtk.c | 157 mux->reg = base + mc->mux_reg; in mtk_clk_register_composite()
|
| /linux-4.4.14/arch/arm/mach-omap1/ |
| D | mux.c | 355 if (cfg->mux_reg) { in omap1_cfg_reg()
359 reg_orig = omap_readl(cfg->mux_reg); in omap1_cfg_reg()
372 omap_writel(reg, cfg->mux_reg); in omap1_cfg_reg()
431 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in omap1_cfg_reg()
|
| /linux-4.4.14/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx6ul-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx7d-pinctrl.txt | 32 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
|
| /linux-4.4.14/arch/arm/mach-davinci/include/mach/ |
| D | mux.h | 25 const unsigned char mux_reg; member
|
| /linux-4.4.14/drivers/pinctrl/sirf/ |
| D | pinctrl-atlas7.c | 187 u32 mux_reg; member
202 .mux_reg = mr, \
5069 pmx->regs[bank] + CLR_REG(conf->mux_reg)); in __atlas7_pmx_pin_enable()
5072 regv = readl(pmx->regs[bank] + conf->mux_reg); in __atlas7_pmx_pin_enable()
5075 pmx->regs[bank] + conf->mux_reg); in __atlas7_pmx_pin_enable()
5077 regv = readl(pmx->regs[bank] + conf->mux_reg); in __atlas7_pmx_pin_enable()
5079 bank, conf->mux_reg, regv); in __atlas7_pmx_pin_enable()
5457 regv = readl(pmx->regs[bank] + conf->mux_reg); in atlas7_pinmux_suspend_noirq()
|