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Searched refs:mt7601u_rr (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/net/wireless/mediatek/mt7601u/
Dcore.c26 val = mt7601u_rr(dev, MT_MAC_CSR0); in mt7601u_wait_asic_ready()
46 cur = mt7601u_rr(dev, offset) & mask; in mt76_poll()
68 cur = mt7601u_rr(dev, offset) & mask; in mt76_poll_msec()
Dinit.c51 val = mt7601u_rr(dev, MT_CMB_CTRL); in mt7601u_set_wlan_state()
73 val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); in mt7601u_chip_onoff()
229 mt7601u_rr(dev, MT_RX_STA_CNT0); in mt7601u_reset_counters()
230 mt7601u_rr(dev, MT_RX_STA_CNT1); in mt7601u_reset_counters()
231 mt7601u_rr(dev, MT_RX_STA_CNT2); in mt7601u_reset_counters()
232 mt7601u_rr(dev, MT_TX_STA_CNT0); in mt7601u_reset_counters()
233 mt7601u_rr(dev, MT_TX_STA_CNT1); in mt7601u_reset_counters()
234 mt7601u_rr(dev, MT_TX_STA_CNT2); in mt7601u_reset_counters()
Dusb.c132 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset) in mt7601u_rr() function
183 val |= mt7601u_rr(dev, offset) & ~mask; in mt7601u_rmw()
190 u32 reg = mt7601u_rr(dev, offset); in mt7601u_rmc()
280 asic_rev = mt7601u_rr(dev, MT_ASIC_VERSION); in mt7601u_probe()
281 mac_rev = mt7601u_rr(dev, MT_MAC_CSR0); in mt7601u_probe()
286 if (!(mt7601u_rr(dev, MT_EFUSE_CTRL) & MT_EFUSE_CTRL_SEL)) in mt7601u_probe()
Deeprom.c178 val = mt7601u_rr(dev, MT_TX_ALC_CFG_0); in mt7601u_set_channel_power()
269 val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_1) & 0x0000ff00) >> 8); in mt7601u_extra_power_over_mac()
270 val |= ((mt7601u_rr(dev, MT_TX_PWR_CFG_2) & 0x0000ff00) << 8); in mt7601u_extra_power_over_mac()
273 val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8); in mt7601u_extra_power_over_mac()
Dphy.c84 val = mt7601u_rr(dev, MT_RF_CSR_CFG); in mt7601u_rf_rr()
173 val = mt7601u_rr(dev, MT_BBP_CSR_CFG); in mt7601u_bbp_rr()
504 rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); in mt7601u_read_bootup_temp()
505 rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); in mt7601u_read_bootup_temp()
565 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_rxdc_cal()
941 val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); in mt7601u_tssi_cal()
1125 mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_init_cal()
1186 old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); in mt7601u_bbp_set_bw()
1223 dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); in mt7601u_phy_init()
1224 dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); in mt7601u_phy_init()
Dmac.c154 val = mt7601u_rr(dev, MT_TX_STAT_FIFO); in mt7601u_mac_fetch_tx_status()
261 u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG); in mt7601u_mac_config_tsf()
281 u32 val = mt7601u_rr(dev, 0x10f4); in mt7601u_check_mac_err()
323 u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4); in mt7601u_mac_work()
543 val = mt7601u_rr(dev, MT_WCID_ATTR(idx)); in mt76_mac_wcid_set_key()
Dmt7601u.h287 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset);
306 return mt7601u_rr(dev, offset); in mt76_rr()
Dmcu.c34 return mt7601u_rr(dev, MT_MCU_COM_REG0) == 1; in firmware_running()
329 val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); in __mt7601u_dma_fw()