Home
last modified time | relevance | path

Searched refs:mmSRBM_SOFT_RESET (Results 1 – 25 of 25) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dcik_ih.c411 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
414 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_ih_soft_reset()
415 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
420 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_ih_soft_reset()
421 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
Dcz_ih.c389 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
392 WREG32(mmSRBM_SOFT_RESET, tmp); in cz_ih_soft_reset()
393 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
398 WREG32(mmSRBM_SOFT_RESET, tmp); in cz_ih_soft_reset()
399 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
Diceland_ih.c389 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
392 WREG32(mmSRBM_SOFT_RESET, tmp); in iceland_ih_soft_reset()
393 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
398 WREG32(mmSRBM_SOFT_RESET, tmp); in iceland_ih_soft_reset()
399 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
Dtonga_ih.c412 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
415 WREG32(mmSRBM_SOFT_RESET, tmp); in tonga_ih_soft_reset()
416 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
421 WREG32(mmSRBM_SOFT_RESET, tmp); in tonga_ih_soft_reset()
422 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
Dgmc_v8_0.c1211 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1214 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1215 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
1220 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v8_0_soft_reset()
1221 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v8_0_soft_reset()
Dvi.c830 tmp = RREG32(mmSRBM_SOFT_RESET); in vi_gpu_soft_reset()
833 WREG32(mmSRBM_SOFT_RESET, tmp); in vi_gpu_soft_reset()
834 tmp = RREG32(mmSRBM_SOFT_RESET); in vi_gpu_soft_reset()
839 WREG32(mmSRBM_SOFT_RESET, tmp); in vi_gpu_soft_reset()
840 tmp = RREG32(mmSRBM_SOFT_RESET); in vi_gpu_soft_reset()
Dgmc_v7_0.c1252 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1255 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1256 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
1261 WREG32(mmSRBM_SOFT_RESET, tmp); in gmc_v7_0_soft_reset()
1262 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v7_0_soft_reset()
Dcik_sdma.c1138 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_sdma_soft_reset()
1141 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_sdma_soft_reset()
1142 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_sdma_soft_reset()
1147 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_sdma_soft_reset()
1148 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_sdma_soft_reset()
Dsdma_v2_4.c1152 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v2_4_soft_reset()
1155 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v2_4_soft_reset()
1156 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v2_4_soft_reset()
1161 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v2_4_soft_reset()
1162 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v2_4_soft_reset()
Dsdma_v3_0.c1314 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v3_0_soft_reset()
1317 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v3_0_soft_reset()
1318 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v3_0_soft_reset()
1323 WREG32(mmSRBM_SOFT_RESET, tmp); in sdma_v3_0_soft_reset()
1324 tmp = RREG32(mmSRBM_SOFT_RESET); in sdma_v3_0_soft_reset()
Dcik.c1258 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_gpu_soft_reset()
1261 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
1262 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_gpu_soft_reset()
1267 WREG32(mmSRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
1268 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_gpu_soft_reset()
Duvd_v6_0.c325 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v6_0_start()
633 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v6_0_soft_reset()
Duvd_v5_0.c327 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v5_0_start()
641 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v5_0_soft_reset()
Duvd_v4_2.c292 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start()
698 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, in uvd_v4_2_soft_reset()
Dvce_v2_0.c474 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK, in vce_v2_0_soft_reset()
Dvce_v3_0.c494 WREG32_P(mmSRBM_SOFT_RESET, mask, in vce_v3_0_soft_reset()
Ddce_v8_0.c3051 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v8_0_soft_reset()
3054 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v8_0_soft_reset()
3055 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v8_0_soft_reset()
3060 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v8_0_soft_reset()
3061 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v8_0_soft_reset()
Ddce_v11_0.c3136 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3139 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v11_0_soft_reset()
3140 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
3145 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v11_0_soft_reset()
3146 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v11_0_soft_reset()
Ddce_v10_0.c3143 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
3146 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset()
3147 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
3152 WREG32(mmSRBM_SOFT_RESET, tmp); in dce_v10_0_soft_reset()
3153 tmp = RREG32(mmSRBM_SOFT_RESET); in dce_v10_0_soft_reset()
Dgfx_v8_0.c4361 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
4364 WREG32(mmSRBM_SOFT_RESET, tmp); in gfx_v8_0_soft_reset()
4365 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
4370 WREG32(mmSRBM_SOFT_RESET, tmp); in gfx_v8_0_soft_reset()
4371 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v8_0_soft_reset()
Dgfx_v7_0.c5276 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5279 WREG32(mmSRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
5280 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
5285 WREG32(mmSRBM_SOFT_RESET, tmp); in gfx_v7_0_soft_reset()
5286 tmp = RREG32(mmSRBM_SOFT_RESET); in gfx_v7_0_soft_reset()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h83 #define mmSRBM_SOFT_RESET 0x398 macro
Doss_3_0_1_d.h81 #define mmSRBM_SOFT_RESET 0x398 macro
Doss_3_0_d.h93 #define mmSRBM_SOFT_RESET 0x398 macro
Doss_2_0_d.h77 #define mmSRBM_SOFT_RESET 0x398 macro