Searched refs:mci_writel (Results 1 - 3 of 3) sorted by relevance

/linux-4.4.14/drivers/mmc/host/
H A Ddw_mmc-exynos.c100 mci_writel(host, MPSBEGIN0, 0); dw_mci_exynos_priv_init()
101 mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX); dw_mci_exynos_priv_init()
102 mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT | dw_mci_exynos_priv_init()
112 mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en); dw_mci_exynos_priv_init()
145 mci_writel(host, CLKSEL64, clksel); dw_mci_exynos_set_clksel_timing()
147 mci_writel(host, CLKSEL, clksel); dw_mci_exynos_set_clksel_timing()
192 mci_writel(host, CLKSEL64, clksel); dw_mci_exynos_resume_noirq()
194 mci_writel(host, CLKSEL, clksel); dw_mci_exynos_resume_noirq()
247 mci_writel(host, HS400_DQS_EN, dqs); dw_mci_exynos_config_hs400()
248 mci_writel(host, HS400_DLINE_CTRL, strobe); dw_mci_exynos_config_hs400()
394 mci_writel(host, CLKSEL64, clksel); dw_mci_exynos_set_clksmpl()
396 mci_writel(host, CLKSEL, clksel); dw_mci_exynos_set_clksmpl()
416 mci_writel(host, CLKSEL64, clksel); dw_mci_exynos_move_next_clksmpl()
418 mci_writel(host, CLKSEL, clksel); dw_mci_exynos_move_next_clksmpl()
461 mci_writel(host, TMOUT, ~0); dw_mci_exynos_execute_tuning()
H A Ddw_mmc.c275 mci_writel(host, CLKENA, clk_en_a); dw_mci_prepare_command()
374 mci_writel(host, CMDARG, cmd->arg); dw_mci_start_command()
378 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); dw_mci_start_command()
425 mci_writel(host, BMOD, bmod); dw_mci_idmac_reset()
436 mci_writel(host, CTRL, temp); dw_mci_idmac_stop_dma()
442 mci_writel(host, BMOD, temp); dw_mci_idmac_stop_dma()
586 mci_writel(host, CTRL, temp); dw_mci_idmac_start_dma()
594 mci_writel(host, BMOD, temp); dw_mci_idmac_start_dma()
597 mci_writel(host, PLDMND, 1); dw_mci_idmac_start_dma()
655 mci_writel(host, IDSTS64, IDMAC_INT_CLR); dw_mci_idmac_init()
656 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | dw_mci_idmac_init()
660 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); dw_mci_idmac_init()
661 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); dw_mci_idmac_init()
665 mci_writel(host, IDSTS, IDMAC_INT_CLR); dw_mci_idmac_init()
666 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | dw_mci_idmac_init()
670 mci_writel(host, DBADDR, host->sg_dma); dw_mci_idmac_init()
901 mci_writel(host, FIFOTH, fifoth_val); dw_mci_adjust_fifoth()
936 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); dw_mci_ctrl_rd_thld()
940 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); dw_mci_ctrl_rd_thld()
981 mci_writel(host, CTRL, temp); dw_mci_submit_data_dma()
987 mci_writel(host, INTMASK, temp); dw_mci_submit_data_dma()
1029 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); dw_mci_submit_data()
1034 mci_writel(host, INTMASK, temp); dw_mci_submit_data()
1039 mci_writel(host, CTRL, temp); dw_mci_submit_data()
1046 mci_writel(host, FIFOTH, host->fifoth_val); dw_mci_submit_data()
1064 mci_writel(host, CMDARG, arg); mci_send_cmd()
1067 mci_writel(host, CMD, SDMMC_CMD_START | cmd); mci_send_cmd()
1092 mci_writel(host, CLKENA, 0); dw_mci_setup_bus()
1113 mci_writel(host, CLKENA, 0); dw_mci_setup_bus()
1114 mci_writel(host, CLKSRC, 0); dw_mci_setup_bus()
1120 mci_writel(host, CLKDIV, div); dw_mci_setup_bus()
1129 mci_writel(host, CLKENA, clk_en_a); dw_mci_setup_bus()
1141 mci_writel(host, CTYPE, (slot->ctype << slot->id)); dw_mci_setup_bus()
1165 mci_writel(host, TMOUT, 0xFFFFFFFF); __dw_mci_start_request()
1166 mci_writel(host, BYTCNT, data->blksz*data->blocks); __dw_mci_start_request()
1167 mci_writel(host, BLKSIZ, data->blksz); __dw_mci_start_request()
1302 mci_writel(slot->host, UHS_REG, regs); dw_mci_set_ios()
1329 mci_writel(slot->host, PWREN, regs); dw_mci_set_ios()
1368 mci_writel(slot->host, PWREN, regs); dw_mci_set_ios()
1425 mci_writel(host, UHS_REG, uhs); dw_mci_switch_voltage()
1507 mci_writel(host, CLKENA, clk_en_a); dw_mci_init_card()
1529 mci_writel(host, INTMASK, int_mask); dw_mci_enable_sdio_irq()
2248 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); dw_mci_read_data_pio()
2304 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); dw_mci_write_data_pio()
2374 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); dw_mci_interrupt()
2389 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); dw_mci_interrupt()
2397 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); dw_mci_interrupt()
2408 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); dw_mci_interrupt()
2421 mci_writel(host, RINTSTS, SDMMC_INT_RXDR); dw_mci_interrupt()
2427 mci_writel(host, RINTSTS, SDMMC_INT_TXDR); dw_mci_interrupt()
2433 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); dw_mci_interrupt()
2438 mci_writel(host, RINTSTS, SDMMC_INT_CD); dw_mci_interrupt()
2450 mci_writel(host, RINTSTS, dw_mci_interrupt()
2465 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | dw_mci_interrupt()
2467 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); dw_mci_interrupt()
2473 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | dw_mci_interrupt()
2475 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); dw_mci_interrupt()
2736 mci_writel(host, CTRL, ctrl); dw_mci_ctrl_reset()
2774 mci_writel(host, RINTSTS, 0xFFFFFFFF); dw_mci_reset()
2949 mci_writel(host, INTMASK, temp); dw_mci_enable_cd()
3078 mci_writel(host, RINTSTS, 0xFFFFFFFF); dw_mci_probe()
3079 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ dw_mci_probe()
3082 mci_writel(host, TMOUT, 0xFFFFFFFF); dw_mci_probe()
3103 mci_writel(host, FIFOTH, host->fifoth_val); dw_mci_probe()
3106 mci_writel(host, CLKENA, 0); dw_mci_probe()
3107 mci_writel(host, CLKSRC, 0); dw_mci_probe()
3136 mci_writel(host, RINTSTS, 0xFFFFFFFF); dw_mci_probe()
3137 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | dw_mci_probe()
3141 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); dw_mci_probe()
3199 mci_writel(host, RINTSTS, 0xFFFFFFFF); dw_mci_remove()
3200 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ dw_mci_remove()
3203 mci_writel(host, CLKENA, 0); dw_mci_remove()
3204 mci_writel(host, CLKSRC, 0); dw_mci_remove()
3248 mci_writel(host, FIFOTH, host->fifoth_val); dw_mci_resume()
3252 mci_writel(host, TMOUT, 0xFFFFFFFF); dw_mci_resume()
3254 mci_writel(host, RINTSTS, 0xFFFFFFFF); dw_mci_resume()
3255 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | dw_mci_resume()
3258 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); dw_mci_resume()
H A Ddw_mmc.h194 #define mci_writel(dev, reg, value) \ macro

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