Searched refs:link_width (Results 1 – 11 of 11) sorted by relevance
345 } link_width; member
1169 u16 link_width = ppd->link_width_active; in active_egress_rate() local1177 switch (link_width) { in active_egress_rate()
561 pi->link_width.enabled = cpu_to_be16(ppd->link_width_enabled); in __subn_get_opa_portinfo()562 pi->link_width.supported = cpu_to_be16(ppd->link_width_supported); in __subn_get_opa_portinfo()563 pi->link_width.active = cpu_to_be16(ppd->link_width_active); in __subn_get_opa_portinfo()1167 lwe = be16_to_cpu(pi->link_width.enabled); in __subn_set_opa_portinfo()
754 int link_width; member
1774 ha->link_width = (lnk >> 4) & 0x3f; in qla4_82xx_start_firmware()
3399 int link_width; in myri10ge_select_firmware() local3403 link_width = (lnk >> 4) & 0x3f; in myri10ge_select_firmware()3408 if (link_width < 8) { in myri10ge_select_firmware()3410 link_width); in myri10ge_select_firmware()
1135 static DEVICE_ATTR(link_width, S_IRUGO, show_lwid, NULL);
4792 u32 link_width = 0; in ci_get_current_pcie_lane_number() local4794 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()4795 link_width >>= LC_LINK_WIDTH_RD_SHIFT; in ci_get_current_pcie_lane_number()4797 switch (link_width) { in ci_get_current_pcie_lane_number()
4962 u32 link_width = 0; in ci_get_current_pcie_lane_number() local4964 link_width = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL) & in ci_get_current_pcie_lane_number()4966 link_width >>= PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT; in ci_get_current_pcie_lane_number()4968 switch (link_width) { in ci_get_current_pcie_lane_number()
3442 int link_width; member
2530 ha->link_width = (lnk >> 4) & 0x3f; in qla82xx_start_firmware()