| /linux-4.4.14/drivers/gpu/drm/exynos/ |
| D | exynos_dp_core.c | 294 int lane, lane_count, pll_tries, retval; in exynos_dp_link_start() local
296 lane_count = dp->link_train.lane_count; in exynos_dp_link_start()
301 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
306 exynos_dp_set_lane_count(dp, dp->link_train.lane_count); in exynos_dp_link_start()
310 buf[1] = dp->link_train.lane_count; in exynos_dp_link_start()
317 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
343 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
348 lane_count, buf); in exynos_dp_link_start()
361 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in exynos_dp_clock_recovery_ok() argument
366 for (lane = 0; lane < lane_count; lane++) { in exynos_dp_clock_recovery_ok()
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| D | exynos_dp_core.h | 135 enum link_lane_count_type lane_count; member
143 u8 lane_count; member
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| /linux-4.4.14/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 264 uint8_t lane_count; member
900 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
913 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
915 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
919 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
923 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
931 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
936 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
993 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1010 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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| D | mdfld_dsi_dpi.c | 470 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
485 val = lane_count; in mdfld_dsi_dpi_controller_init()
506 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
523 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
749 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
773 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
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| D | mdfld_dsi_output.c | 434 config->lane_count = 4; in mdfld_dsi_get_default_config()
436 config->lane_count = 2; in mdfld_dsi_get_default_config()
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| D | mdfld_dsi_output.h | 260 int lane_count; member
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| /linux-4.4.14/drivers/gpu/drm/i915/ |
| D | intel_dsi_pll.c | 78 int lane_count, bool eotp) in dsi_rr_formula() argument
131 bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; in dsi_rr_formula()
146 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) in dsi_clk_from_pclk() argument
153 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
227 intel_dsi->lane_count); in vlv_configure_dsi_pll()
382 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_get_dsi_pclk()
416 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); in bxt_get_dsi_pclk()
480 intel_dsi->lane_count); in bxt_configure_dsi_pll()
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| D | intel_dsi.c | 761 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
765 8 * 100), lane_count); in txbyteclkhs()
777 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings() local
800 hactive = txbyteclkhs(hactive, bpp, lane_count, in set_dsi_timings()
802 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
803 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
805 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
909 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
950 intel_dsi->lane_count, in intel_dsi_prepare()
956 bpp, intel_dsi->lane_count, in intel_dsi_prepare()
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| D | intel_dp_mst.c | 42 int lane_count, slots; in intel_dp_mst_compute_config() local
57 lane_count = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_mst_compute_config()
60 pipe_config->lane_count = lane_count; in intel_dp_mst_compute_config()
86 intel_link_compute_m_n(bpp, lane_count, in intel_dp_mst_compute_config()
282 pipe_config->lane_count = in intel_dp_mst_enc_get_config()
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| D | intel_dp.c | 133 static unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
135 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
1389 int lane_count, clock; in intel_dp_compute_config() local
1471 for (lane_count = min_lane_count; in intel_dp_compute_config()
1472 lane_count <= max_lane_count; in intel_dp_compute_config()
1473 lane_count <<= 1) { in intel_dp_compute_config()
1477 lane_count); in intel_dp_compute_config()
1502 pipe_config->lane_count = lane_count; in intel_dp_compute_config()
1511 link_bw, rate_select, pipe_config->lane_count, in intel_dp_compute_config()
1516 intel_link_compute_m_n(bpp, lane_count, in intel_dp_compute_config()
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| D | intel_dsi_panel_vbt.c | 413 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in vbt_panel_init()
457 (pclk * bits_per_pixel) / intel_dsi->lane_count; in vbt_panel_init()
480 bitrate = (pclk * bits_per_pixel) / intel_dsi->lane_count; in vbt_panel_init()
498 switch (intel_dsi->lane_count) { in vbt_panel_init()
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| D | intel_dsi.h | 63 unsigned int lane_count; member
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| D | intel_drv.h | 439 uint8_t lane_count; member
733 uint8_t lane_count; member
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| D | intel_ddi.c | 734 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); in intel_ddi_init_dp_buf_reg()
1933 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); in intel_ddi_enable_transcoder_func()
1942 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); in intel_ddi_enable_transcoder_func()
3162 pipe_config->lane_count = in intel_ddi_get_config()
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| D | intel_hdmi.c | 1657 if (crtc->config->lane_count > 2) { in chv_data_lane_soft_reset()
1674 if (crtc->config->lane_count > 2) { in chv_data_lane_soft_reset()
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| D | intel_display.c | 12020 pipe_config->lane_count, in intel_dump_pipe_config()
12027 pipe_config->lane_count, in intel_dump_pipe_config()
12534 PIPE_CONF_CHECK_I(lane_count); in intel_pipe_config_compare()
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| /linux-4.4.14/drivers/gpu/drm/bridge/ |
| D | parade-ps8622.c | 66 u32 lane_count; member
202 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
610 &ps8622->lane_count)) { in ps8622_probe()
611 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
612 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
615 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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| /linux-4.4.14/drivers/gpu/drm/ |
| D | drm_dp_helper.c | 58 int lane_count) in drm_dp_channel_eq_ok() argument
68 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
78 int lane_count) in drm_dp_clock_recovery_ok() argument
83 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
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| /linux-4.4.14/include/drm/ |
| D | drm_dp_helper.h | 577 int lane_count);
579 int lane_count);
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | atombios_dp.c | 208 int lane_count, in amdgpu_atombios_dp_get_adjust_train() argument
215 for (lane = 0; lane < lane_count; lane++) { in amdgpu_atombios_dp_get_adjust_train()
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| /linux-4.4.14/drivers/edac/ |
| D | ppc4xx_edac.c | 444 const unsigned int lane_count = 16; in ppc4xx_edac_generate_lane_message() local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()
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| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 259 int lane_count, in dp_get_adjust_train() argument
266 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()
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