Searched refs:iccr (Results 1 - 5 of 5) sorted by relevance

/linux-4.4.14/arch/sparc/include/asm/
H A Dross.h81 * Wheee, not many assemblers understand the %iccr register nor
84 * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
88 * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
103 __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */ get_ross_icr()
115 ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */ put_ross_icr()
H A Dleon.h211 unsigned long iccr; /* 0x08 - Instruction Cache Configuration Register */ member in struct:leon3_cacheregs
/linux-4.4.14/drivers/irqchip/
H A Dirq-sa11x0.c88 unsigned int iccr; member in struct:sa1100irq_state
98 st->iccr = readl_relaxed(iobase + ICCR); sa1100irq_suspend()
113 writel_relaxed(st->iccr, iobase + ICCR); sa1100irq_resume()
/linux-4.4.14/arch/sparc/mm/
H A Dleon_mm.c217 unsigned long ccr, iccr, dccr; leon3_getCacheRegs() local
227 : "=r"(ccr), "=r"(iccr), "=r"(dccr) leon3_getCacheRegs()
233 regs->iccr = iccr; leon3_getCacheRegs()
/linux-4.4.14/arch/unicore32/kernel/
H A Dirq.c235 unsigned int iccr; member in struct:puv3_irq_state
245 st->iccr = readl(INTC_ICCR); puv3_irq_suspend()
271 writel(st->iccr, INTC_ICCR); puv3_irq_resume()

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