Searched refs:gb_tiling_config (Results 1 - 2 of 2) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dr600_cp.c748 u32 gb_tiling_config = 0; r600_gfx_init() local
841 gb_tiling_config |= R600_PIPE_TILING(0); r600_gfx_init()
844 gb_tiling_config |= R600_PIPE_TILING(1); r600_gfx_init()
847 gb_tiling_config |= R600_PIPE_TILING(2); r600_gfx_init()
850 gb_tiling_config |= R600_PIPE_TILING(3); r600_gfx_init()
856 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); r600_gfx_init()
858 gb_tiling_config |= R600_GROUP_SIZE(0); r600_gfx_init()
861 gb_tiling_config |= R600_ROW_TILING(3); r600_gfx_init()
862 gb_tiling_config |= R600_SAMPLE_SPLIT(3); r600_gfx_init()
864 gb_tiling_config |= r600_gfx_init()
866 gb_tiling_config |= r600_gfx_init()
870 gb_tiling_config |= R600_BANK_SWAPS(1); r600_gfx_init()
887 gb_tiling_config |= R600_BACKEND_MAP(backend_map); r600_gfx_init()
889 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); r600_gfx_init()
890 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); r600_gfx_init()
891 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); r600_gfx_init()
892 if (gb_tiling_config & 0xc0) { r600_gfx_init()
897 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); r600_gfx_init()
898 if (gb_tiling_config & 0x30) { r600_gfx_init()
1372 u32 gb_tiling_config = 0; r700_gfx_init() local
1491 gb_tiling_config |= R600_PIPE_TILING(0); r700_gfx_init()
1494 gb_tiling_config |= R600_PIPE_TILING(1); r700_gfx_init()
1497 gb_tiling_config |= R600_PIPE_TILING(2); r700_gfx_init()
1500 gb_tiling_config |= R600_PIPE_TILING(3); r700_gfx_init()
1507 gb_tiling_config |= R600_BANK_TILING(1); r700_gfx_init()
1509 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); r700_gfx_init()
1511 gb_tiling_config |= R600_GROUP_SIZE(0); r700_gfx_init()
1514 gb_tiling_config |= R600_ROW_TILING(3); r700_gfx_init()
1515 gb_tiling_config |= R600_SAMPLE_SPLIT(3); r700_gfx_init()
1517 gb_tiling_config |= r700_gfx_init()
1519 gb_tiling_config |= r700_gfx_init()
1523 gb_tiling_config |= R600_BANK_SWAPS(1); r700_gfx_init()
1544 gb_tiling_config |= R600_BACKEND_MAP(backend_map); r700_gfx_init()
1546 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); r700_gfx_init()
1547 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); r700_gfx_init()
1548 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); r700_gfx_init()
1549 if (gb_tiling_config & 0xc0) { r700_gfx_init()
1554 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); r700_gfx_init()
1555 if (gb_tiling_config & 0x30) { r700_gfx_init()
H A Drv770.c1179 u32 gb_tiling_config = 0; rv770_gpu_init() local
1321 gb_tiling_config = PIPE_TILING(0); rv770_gpu_init()
1324 gb_tiling_config = PIPE_TILING(1); rv770_gpu_init()
1327 gb_tiling_config = PIPE_TILING(2); rv770_gpu_init()
1330 gb_tiling_config = PIPE_TILING(3); rv770_gpu_init()
1344 tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; rv770_gpu_init()
1347 gb_tiling_config |= tmp << 16; rv770_gpu_init()
1351 gb_tiling_config |= BANK_TILING(1); rv770_gpu_init()
1354 gb_tiling_config |= BANK_TILING(1); rv770_gpu_init()
1356 gb_tiling_config |= BANK_TILING(0); rv770_gpu_init()
1358 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3); rv770_gpu_init()
1359 gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); rv770_gpu_init()
1361 gb_tiling_config |= ROW_TILING(3); rv770_gpu_init()
1362 gb_tiling_config |= SAMPLE_SPLIT(3); rv770_gpu_init()
1364 gb_tiling_config |= rv770_gpu_init()
1366 gb_tiling_config |= rv770_gpu_init()
1370 gb_tiling_config |= BANK_SWAPS(1); rv770_gpu_init()
1371 rdev->config.rv770.tile_config = gb_tiling_config; rv770_gpu_init()
1373 WREG32(GB_TILING_CONFIG, gb_tiling_config); rv770_gpu_init()
1374 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); rv770_gpu_init()
1375 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); rv770_gpu_init()
1376 WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); rv770_gpu_init()
1377 WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); rv770_gpu_init()
1379 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); rv770_gpu_init()
1380 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); rv770_gpu_init()
1381 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); rv770_gpu_init()

Completed in 61 milliseconds