1179 	u32 gb_tiling_config = 0;  in rv770_gpu_init()  local
1321 		gb_tiling_config = PIPE_TILING(0);  in rv770_gpu_init()
1324 		gb_tiling_config = PIPE_TILING(1);  in rv770_gpu_init()
1327 		gb_tiling_config = PIPE_TILING(2);  in rv770_gpu_init()
1330 		gb_tiling_config = PIPE_TILING(3);  in rv770_gpu_init()
1344 	tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;  in rv770_gpu_init()
1347 	gb_tiling_config |= tmp << 16;  in rv770_gpu_init()
1351 		gb_tiling_config |= BANK_TILING(1);  in rv770_gpu_init()
1354 			gb_tiling_config |= BANK_TILING(1);  in rv770_gpu_init()
1356 			gb_tiling_config |= BANK_TILING(0);  in rv770_gpu_init()
1358 	rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);  in rv770_gpu_init()
1359 	gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);  in rv770_gpu_init()
1361 		gb_tiling_config |= ROW_TILING(3);  in rv770_gpu_init()
1362 		gb_tiling_config |= SAMPLE_SPLIT(3);  in rv770_gpu_init()
1364 		gb_tiling_config |=  in rv770_gpu_init()
1366 		gb_tiling_config |=  in rv770_gpu_init()
1370 	gb_tiling_config |= BANK_SWAPS(1);  in rv770_gpu_init()
1371 	rdev->config.rv770.tile_config = gb_tiling_config;  in rv770_gpu_init()
1373 	WREG32(GB_TILING_CONFIG, gb_tiling_config);  in rv770_gpu_init()
1374 	WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1375 	WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1376 	WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1377 	WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1379 		WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1380 		WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()
1381 		WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));  in rv770_gpu_init()