Searched refs:g5 (Results 1 - 61 of 61) sorted by relevance

/linux-4.4.14/arch/sparc/kernel/
H A Dktlb.S29 sethi %hi(PAGE_SIZE), %g5
30 cmp %g4, %g5
34 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
37 sethi %hi(LOW_OBP_ADDRESS), %g5
38 cmp %g4, %g5
40 mov 0x1, %g5
41 sllx %g5, 32, %g5
42 cmp %g4, %g5
47 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
50 TSB_WRITE(%g1, %g5, %g6)
56 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
70 * %g5: PTE
77 mov %g5, %g3
81 661: rdpr %pstate, %g5
82 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
89 rdpr %tpc, %g5
94 OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
98 TSB_WRITE(%g1, %g5, %g6)
104 OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
108 TSB_WRITE(%g1, %g5, %g6)
117 xor %g2, %g4, %g5
122 TSB_WRITE(%g1, %g5, %g6)
142 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
145 KERN_TSB4M_LOOKUP_TL1(%g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
155 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
158 TSB_WRITE(%g1, %g5, %g6)
164 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
178 * %g5: PTE
185 mov %g5, %g3
189 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
195 sethi %hi(PAGE_SIZE), %g5
196 cmp %g4, %g5
202 sethi %hi(VMEMMAP_BASE), %g5
203 ldx [%g5 + %lo(VMEMMAP_BASE)], %g5
204 cmp %g4,%g5
209 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
212 sethi %hi(MODULES_VADDR), %g5
213 cmp %g4, %g5
215 sethi %hi(VMALLOC_END), %g5
216 ldx [%g5 + %lo(VMALLOC_END)], %g5
217 cmp %g4, %g5
222 sethi %hi(LOW_OBP_ADDRESS), %g5
223 cmp %g4, %g5
225 mov 0x1, %g5
226 sllx %g5, 32, %g5
227 cmp %g4, %g5
235 661: rdpr %pstate, %g5
236 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
240 ldxa [%g0] ASI_SCRATCHPAD, %g5
247 ldxa [%g4] ASI_DMMU, %g5
250 ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
H A Dsun4v_tlb_miss.S54 LOAD_ITLB_INFO(%g2, %g4, %g5)
55 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
77 mov %o2, %g5 ! save %o2
87 mov %g5, %o2 ! restore %o2
100 LOAD_DTLB_INFO(%g2, %g4, %g5)
101 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
120 mov %o2, %g5 ! save %o2
130 mov %g5, %o2 ! restore %o2
138 /* Load MMU Miss base into %g5. */
139 ldxa [%g0] ASI_SCRATCHPAD, %g5
141 ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
151 * %g5: context
157 brz,pn %g5, kvmap_itlb_4v
163 * %g5: context
169 brz,pn %g5, kvmap_dtlb_4v
175 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)
180 mov SCRATCHPAD_UTSBREG2, %g5
181 ldxa [%g5] ASI_SCRATCHPAD, %g5
182 cmp %g5, -1
185 COMPUTE_TSB_PTR(%g5, %g4, REAL_HPAGE_SHIFT, %g2, %g7)
191 80: stx %g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
252 or %g0, %g4, %g5
263 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
265 or %g5, %g3, %g5
279 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
281 or %g5, %g3, %g5
295 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
297 or %g5, %g3, %g5
311 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
313 or %g5, %g3, %g5
332 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
344 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
346 or %g5, %g3, %g5
369 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
371 or %g5, %g3, %g5
385 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
387 or %g5, %g3, %g5
H A Dtrampoline_32.S59 set current_set, %g5
62 ld [%g5 + %g4], %g6
74 set poke_srmmu, %g5
75 ld [%g5], %g5
76 call %g5
121 set current_set, %g5
123 ld [%g5 + %g4], %g6
135 set poke_srmmu, %g5
136 ld [%g5], %g5
137 call %g5
154 set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
155 sta %g1, [%g5] ASI_LEON_MMUREGS
176 set current_set, %g5
179 ld [%g5 + %g4], %g6
191 set poke_srmmu, %g5
192 ld [%g5], %g5
193 call %g5
H A Divec.S4 * [high 32-bits] MMU Context Argument 0, place in %g5
20 srlx %g3, 32, %g5
31 ldx [%g6], %g5
32 stxa %g5, [%g3] ASI_PHYS_USE_EC
H A Dtsb.S24 * %g5: available temporary
47 TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
54 661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
58 mov SCRATCHPAD_UTSBREG2, %g5
59 ldxa [%g5] ASI_SCRATCHPAD, %g5
62 cmp %g5, -1
74 and %g5, 0x7, %g6
76 andn %g5, 0x7, %g5
82 add %g5, %g6, %g5
84 TSB_LOAD_QUAD(%g5, %g6)
87 mov %g7, %g5
94 80: stx %g5, [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP]
111 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
113 /* Valid PTE is now in %g5. */
124 and %g5, %g7, %g2
157 661: rdpr %pstate, %g5
158 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
182 * %g5 -- valid PTE
187 TSB_WRITE(%g1, %g5, %g6)
197 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN
211 * %g5: PTE
218 mov %g5, %g3
223 andcc %g5, %g4, %g0
226 andcc %g5, _PAGE_EXEC_4V, %g0
233 661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
247 * %g5: PTE
254 mov %g5, %g3
264 661: rdpr %pstate, %g5
265 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
280 ldxa [%g4] ASI_DMMU, %g5
283 ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
293 rdpr %tpc, %g5
299 /* fault code in %g4, fault address in %g5, etrap will
H A Dsun4v_ivec.S36 * high half is context arg to MMU flushes, into %g5
42 srlx %g3, 32, %g5
77 /* Get DEV mondo queue base phys address into %g5. */
78 ldx [%g4 + TRAP_PER_CPU_DEV_MONDO_PA], %g5
81 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
135 /* Get RES mondo queue base phys address into %g5. */
136 ldx [%g3 + TRAP_PER_CPU_RESUM_MONDO_PA], %g5
152 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
155 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
158 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
161 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
164 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
167 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
170 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
173 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
246 /* Get RES mondo queue base phys address into %g5. */
247 ldx [%g3 + TRAP_PER_CPU_NONRESUM_MONDO_PA], %g5
263 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
266 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
269 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
272 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
275 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
278 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
281 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
284 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
H A Dhvtramp.S108 mov 1, %g5
109 sllx %g5, THREAD_SHIFT, %g5
110 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
111 add %g6, %g5, %sp
H A Dtrampoline_64.S43 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
44 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
58 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
59 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
60 sllx %g5, 32, %g5
61 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
62 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
84 sethi %hi(0x80000000), %g5
85 sllx %g5, 32, %g5
86 wr %g5, %asr25
136 BRANCH_IF_ANY_CHEETAH(g1,g5,2f)
277 * %g4 (current task pointer), or %g5 (base of current cpu's
291 set 0xdeadbeef, %g5
396 mov 1, %g5
397 sllx %g5, THREAD_SHIFT, %g5
398 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
399 add %g6, %g5, %sp
H A Dfpu_traps.S6 rdpr %tstate, %g5
7 andcc %g5, %g4, %g0
10 rd %fprs, %g5
11 andcc %g5, FPRS_FEF, %g0
23 ldub [%g6 + TI_FPSAVED], %g5
25 andcc %g5, FPRS_FEF, %g0
29 1: andcc %g5, FPRS_DL, %g0
32 andcc %g5, FPRS_DU, %g0
70 661: ldxa [%g3] ASI_DMMU, %g5
73 ldxa [%g3] ASI_MMU, %g5
105 2: andcc %g5, FPRS_DU, %g0
111 661: ldxa [%g3] ASI_DMMU, %g5
114 ldxa [%g3] ASI_MMU, %g5
152 661: ldxa [%g3] ASI_DMMU, %g5
155 ldxa [%g3] ASI_MMU, %g5
178 661: stxa %g5, [%g3] ASI_DMMU
181 stxa %g5, [%g3] ASI_MMU
344 661: ldxa [%g3] ASI_DMMU, %g5
347 ldxa [%g3] ASI_MMU, %g5
374 661: stxa %g5, [%g1] ASI_DMMU
377 stxa %g5, [%g1] ASI_MMU
H A Dmisctrap.S29 /* Setup %g4/%g5 now as they are used in the
35 ldxa [%g3] ASI_DMMU, %g5
55 ldxa [%g4] ASI_DMMU, %g5
73 ldxa [%g4] ASI_DMMU, %g5
H A Durtt_fill.S35 mov %g5, %l5
41 stx %g5, [%g6 + TI_FAULT_ADDR]
56 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
H A Dhead_32.S126 set current_pc, %g5
127 cmp %g3, %g5
255 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
257 or %g5, %g6, %g6 ! Or it in...
288 /* Ok, restore the MMU control register we saved in %g5 */
289 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
450 set sun4d_handler_irq, %g5
452 sub %g5, %g4, %g5
453 srl %g5, 2, %g5
454 or %g5, %g3, %g5
455 st %g5, [%g4]
464 sethi %hi(boot_cpu_id), %g5
465 stb %g4, [%g5 + %lo(boot_cpu_id)]
585 set src, %g5; \
587 ld [%g5], %g4; \
621 set flush_patch_one, %g5
622 st %g4, [%g5 + 0x18]
623 st %g4, [%g5 + 0x1c]
624 set flush_patch_two, %g5
625 st %g4, [%g5 + 0x18]
626 st %g4, [%g5 + 0x1c]
627 set flush_patch_three, %g5
628 st %g4, [%g5 + 0x18]
629 st %g4, [%g5 + 0x1c]
630 set flush_patch_four, %g5
631 st %g4, [%g5 + 0x18]
632 st %g4, [%g5 + 0x1c]
633 set flush_patch_exception, %g5
634 st %g4, [%g5 + 0x18]
635 st %g4, [%g5 + 0x1c]
636 set flush_patch_switch, %g5
637 st %g4, [%g5 + 0x18]
638 st %g4, [%g5 + 0x1c]
661 sethi %hi(prom_vector_p), %g5
662 ld [%g5 + %lo(prom_vector_p)], %o0
H A Dspiterrs.S24 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
160 mov DMMU_SFAR, %g5
162 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
188 mov DMMU_SFAR, %g5
190 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
209 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
228 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
H A Dasm-offsets.c39 OFFSET(SC_REG_G5, saved_context, g5); sparc64_foo()
H A Dwinfixup.S29 stx %g5, [%g6 + TI_FAULT_ADDR]
38 * You cannot touch %g5 as that has the fault information.
98 stx %g5, [%g6 + TI_FAULT_ADDR]
H A Dwindows.c21 register int ctr asm("g5"); flush_user_windows()
104 "g2", "g3", "g4", "g5");
H A Detrap_64.S25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
115 mov %g5, %l5
131 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
148 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
H A Dcherrs.S298 * %g5: AFAR
337 stx %g5, [%g1 + 0x8]
342 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
343 srlx %g5, 12, %g3
385 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
387 srlx %g5, (13 - 8), %g3 /* Make PTAG */
434 30: andn %g5, (32 - 1), %g2
480 ldxa [%g0] ASI_AFAR, %g5
516 ldxa [%g0] ASI_AFAR, %g5
552 ldxa [%g0] ASI_AFAR, %g5
H A Dwof.S43 #define glob_tmp g5 /* Global temporary reg, usable anywhere G */
75 mov %g5, %saved_g5 ! save away global temp register
119 mov %saved_g5, %g5 ! restore %glob_tmp
187 mov %saved_g5, %g5
243 mov %saved_g5, %g5
282 mov %saved_g5, %g5
H A Dwuf.S182 mov 0x1, %g5
183 sll %g5, %g3, %g5
184 st %g5, [%curptr + TI_UWINMASK] ! one live user window still
H A Drtrap_64.S160 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
165 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
H A Dentry.S886 rd %wim, %g5
907 rd %wim, %g5
927 rd %wim, %g5
H A Dsignal_32.c471 * In particular %g2, %g3, %g4, and %g5 are all assumed to be do_signal()
H A Dprocess_64.c177 printk("g4: %016lx g5: %016lx g6: %016lx g7: %016lx\n", show_regs()
H A Dsignal_64.c490 * In particular %g2, %g3, %g4, and %g5 are all assumed to be do_signal()
H A Dhead_64.S680 clr %g5
H A Dsmp_64.c1561 /* Setup %g5 for the boot cpu. */ setup_per_cpu_areas()
/linux-4.4.14/arch/sparc/mm/
H A Dviking.S52 sll %o2, 26, %g5 ! block << 26
54 or %g5, %g4, %g5
55 ldda [%g5] ASI_M_DATAC_TAG, %g2
79 sll %o2, 26, %g5 ! block << 26
122 WINDOW_FLUSH(%g4, %g5)
135 lda [%g1] ASI_M_MMUREGS, %g5
144 sta %g5, [%g1] ASI_M_MMUREGS
154 lda [%g1] ASI_M_MMUREGS, %g5
169 sta %g5, [%g1] ASI_M_MMUREGS
179 lda [%g1] ASI_M_MMUREGS, %g5
188 sta %g5, [%g1] ASI_M_MMUREGS
205 1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
206 tst %g5
212 2: tst %g5
214 ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
219 1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
220 tst %g5
224 lda [%g1] ASI_M_MMUREGS, %g5
228 sta %g5, [%g1] ASI_M_MMUREGS
231 2: tst %g5
233 ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
238 1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
239 tst %g5
244 lda [%g1] ASI_M_MMUREGS, %g5
254 sta %g5, [%g1] ASI_M_MMUREGS
257 3: tst %g5
259 ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
264 1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
265 tst %g5
270 lda [%g1] ASI_M_MMUREGS, %g5
274 sta %g5, [%g1] ASI_M_MMUREGS
277 2: tst %g5
279 ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
H A Dhypersparc.S26 WINDOW_FLUSH(%g4, %g5)
28 ld [%g4 + %lo(vac_cache_size)], %g5
32 subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
34 sta %g0, [%g5] ASI_M_FLUSH_CTX
45 WINDOW_FLUSH(%g4, %g5)
55 add %o1, %g4, %g5
56 add %o1, %g5, %o4
68 sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
83 WINDOW_FLUSH(%g4, %g5)
98 sll %o3, 2, %g5
100 cmp %g4, %g5
103 add %o4, %g4, %g5
104 add %o4, %g5, %g7
119 sta %g0, [%o3 + %g5] ASI_M_FLUSH_USER
136 add %o4, %g5, %g7
148 sta %g0, [%o2 + %g5] ASI_M_FLUSH_PAGE
153 mov SRMMU_FAULT_STATUS, %g5
154 lda [%g5] ASI_M_MMUREGS, %g0
172 WINDOW_FLUSH(%g4, %g5)
190 add %o4, %g4, %g5
191 add %o4, %g5, %g7
205 sta %g0, [%o1 + %g5] ASI_M_FLUSH_PAGE
227 lda [%g7] ASI_M_FLUSH_PROBE, %g5
229 orcc %g5, 0, %g0
235 add %o4, %g4, %g5
236 add %o4, %g5, %g7
250 sta %g0, [%o0 + %g5] ASI_M_FLUSH_PAGE
274 lda [%g1] ASI_M_MMUREGS, %g5
284 sta %g5, [%g1] ASI_M_MMUREGS
290 lda [%g1] ASI_M_MMUREGS, %g5
307 sta %g5, [%g1] ASI_M_MMUREGS
318 lda [%g1] ASI_M_MMUREGS, %g5
323 sta %g5, [%g1] ASI_M_MMUREGS
334 mov 128, %g5
344 stda %g0, [%o0 + %g5] ASI_M_BFILL
H A Dswift.S42 WINDOW_FLUSH(%g4, %g5)
58 WINDOW_FLUSH(%g4, %g5)
65 lda [%g7] ASI_M_MMUREGS, %g5
98 sta %g5, [%g7] ASI_M_MMUREGS
124 WINDOW_FLUSH(%g4, %g5)
131 lda [%g7] ASI_M_MMUREGS, %g5
164 sta %g5, [%g7] ASI_M_MMUREGS
247 lda [%g1] ASI_M_MMUREGS, %g5
251 sta %g5, [%g1] ASI_M_MMUREGS
H A Dultra.S439 * %g5 mm->context (all tlb flushes)
455 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
456 stxa %g5, [%g2] ASI_DMMU
475 /* %g5=context, %g1=vaddr */
480 or %g5, %g4, %g5
482 stxa %g5, [%g4] ASI_DMMU
485 andn %g1, 0x1, %g5
486 stxa %g0, [%g5] ASI_IMMU_DEMAP
487 2: stxa %g0, [%g5] ASI_DMMU_DEMAP
657 %g5 == (page->mapping != NULL) */
676 brz,pn %g5, 2f
689 /* %g5: error
693 mov %g5, %g4
694 mov %g6, %g5
704 /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
712 mov %g5, %o2 /* ARG2: mmu context */
718 mov %o0, %g5
729 /* %g5=ctx, %g1=vaddr */
734 mov %g5, %o1 /* ARG1: mmu context */
741 mov %o0, %g5
750 /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
767 mov %o0, %g5
H A Dtsunami.S33 WINDOW_FLUSH(%g4, %g5)
74 lda [%g1] ASI_M_MMUREGS, %g5
84 sta %g5, [%g1] ASI_M_MMUREGS
/linux-4.4.14/arch/sparc/include/asm/
H A Dpercpu_64.h6 register unsigned long __local_per_cpu_offset asm("g5");
H A Dxor_32.h41 "xor %%g5, %%l1, %%g5\n\t" sparc_2()
52 : "g2", "g3", "g4", "g5", sparc_2()
80 "xor %%g5, %%l1, %%g5\n\t" sparc_3()
91 "xor %%g5, %%l1, %%g5\n\t" sparc_3()
102 : "g2", "g3", "g4", "g5", sparc_3()
131 "xor %%g5, %%l1, %%g5\n\t" sparc_4()
143 "xor %%g5, %%l1, %%g5\n\t" sparc_4()
154 "xor %%g5, %%l1, %%g5\n\t" sparc_4()
165 : "g2", "g3", "g4", "g5", sparc_4()
195 "xor %%g5, %%l1, %%g5\n\t" sparc_5()
207 "xor %%g5, %%l1, %%g5\n\t" sparc_5()
219 "xor %%g5, %%l1, %%g5\n\t" sparc_5()
230 "xor %%g5, %%l1, %%g5\n\t" sparc_5()
241 : "g2", "g3", "g4", "g5", sparc_5()
H A Dhibernate.h19 unsigned long g5; member in struct:saved_context
H A Dswitch_to_32.h67 "rd %%wim, %%g5\n\t" \
81 "wr %%g5, 0x0, %%wim\n\t" \
96 : "g1", "g2", "g3", "g4", "g5", "g7", \
H A Dttable.h198 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
208 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
223 * Further note that we cannot use the g2, g4, g5, and g7 alternate
226 * g4/g5 are the globals which are preserved by etrap processing
546 mov 0x18, %g5; \
548 ldxa [%g1 + %g5] ASI, %l3; \
553 ldxa [%g1 + %g5] ASI, %l7; \
558 ldxa [%g1 + %g5] ASI, %i3; \
563 ldxa [%g1 + %g5] ASI, %i7; \
606 mov 0x0c, %g5; \
608 lduwa [%sp + %g5] ASI, %l3; \
613 lduwa [%g1 + %g5] ASI, %l7; \
618 lduwa [%g1 + %g5] ASI, %i3; \
623 lduwa [%g1 + %g5] ASI, %i7; \
H A Dchecksum_32.h56 "g2", "g3", "g4", "g5", "g7", csum_partial_copy_nocheck()
80 : "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5", csum_partial_copy_from_user()
109 "g2", "g3", "g4", "g5", csum_partial_copy_to_user()
H A Duaccess_32.h359 "g1", "g2", "g3", "g4", "g5", "g7", "cc"); __clear_user()
H A Dtsb.h21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN
/linux-4.4.14/arch/sparc/lib/
H A Dchecksum_32.S114 5: CSUM_BIGCHUNK(%o0, 0x00, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
115 CSUM_BIGCHUNK(%o0, 0x20, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
116 CSUM_BIGCHUNK(%o0, 0x40, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
117 CSUM_BIGCHUNK(%o0, 0x60, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
130 cptbl: CSUM_LASTCHUNK(%o0, 0x68, %o2, %g2, %g3, %g4, %g5)
131 CSUM_LASTCHUNK(%o0, 0x58, %o2, %g2, %g3, %g4, %g5)
132 CSUM_LASTCHUNK(%o0, 0x48, %o2, %g2, %g3, %g4, %g5)
133 CSUM_LASTCHUNK(%o0, 0x38, %o2, %g2, %g3, %g4, %g5)
134 CSUM_LASTCHUNK(%o0, 0x28, %o2, %g2, %g3, %g4, %g5)
135 CSUM_LASTCHUNK(%o0, 0x18, %o2, %g2, %g3, %g4, %g5)
136 CSUM_LASTCHUNK(%o0, 0x08, %o2, %g2, %g3, %g4, %g5)
349 5: CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x00,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
350 CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
351 CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x40,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
352 CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x60,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
371 cctbl: CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x68,%g2,%g3,%g4,%g5)
372 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x58,%g2,%g3,%g4,%g5)
373 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x48,%g2,%g3,%g4,%g5)
374 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x38,%g2,%g3,%g4,%g5)
375 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x28,%g2,%g3,%g4,%g5)
376 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x18,%g2,%g3,%g4,%g5)
377 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x08,%g2,%g3,%g4,%g5)
385 ccdbl: CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x00,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
386 CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
387 CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x40,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
388 CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x60,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
400 mov 0, %g5
406 EX(ldub [%o0], %g5, add %g1, 1)
408 EX2(stb %g5, [%o1])
422 add %o4, %g5, %g5
438 addcc %o4, %g5, %g5
440 addx %g5, %g0, %g5 ! I am now to lazy to optimize this (question it
445 sll %g5, 16, %g2
446 srl %g5, 16, %g5
449 add %g2, %g5, %g5
457 add %g5, %o4, %g5
461 sll %g5, 16, %o4
465 add %g5, %o4, %g5
466 sll %g5, 16, %o4
467 1: addcc %o4, %g5, %g5
468 srl %g5, 16, %o4
469 addx %g0, %o4, %g5
472 srl %g5, 8, %o4
473 and %g5, 0xff, %g2
476 or %g2, %o4, %g5
477 4: addcc %g7, %g5, %g7
H A Dmemcpy.S236 MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
237 MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
238 MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
239 MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
260 MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
261 MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
262 MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
263 MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
264 MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
265 MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
266 MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
306 MOVE_BIGALIGNCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
307 MOVE_BIGALIGNCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
308 MOVE_BIGALIGNCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
309 MOVE_BIGALIGNCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
328 MOVE_LASTALIGNCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
329 MOVE_LASTALIGNCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
330 MOVE_LASTALIGNCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
331 MOVE_LASTALIGNCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
332 MOVE_LASTALIGNCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
333 MOVE_LASTALIGNCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
334 MOVE_LASTALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
382 ldub [%i1], %g5
384 stb %g5, [%i0]
443 srl %g1, %l0, %g5
444 or %g2, %g5, %g2
449 srl %i3, %l0, %g5
450 or %g2, %g5, %g2
455 srl %i4, %l0, %g5
456 or %g2, %g5, %g2
461 srl %i5, %l0, %g5
463 or %g2, %g5, %g2
471 srl %g1, %l0, %g5
473 or %g2, %g5, %g2
H A Dblockops.S74 MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
75 MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
76 MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
77 MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
78 MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
79 MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
80 MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
81 MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
H A Dcopy_user.S178 MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
179 MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
180 MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
181 MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
202 MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
203 MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
204 MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
205 MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
206 MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
207 MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
208 MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
246 MOVE_BIGALIGNCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
247 MOVE_BIGALIGNCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
248 MOVE_BIGALIGNCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
249 MOVE_BIGALIGNCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
288 MOVE_HALFCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
289 MOVE_HALFCHUNK(o1, o0, 0x08, g2, g3, g4, g5)
H A DGENmemcpy.S9 #define GLOBAL_SPARE %g5
H A DNG4memcpy.S26 clr %g1; clr %g2; clr %g3; clr %g5; subcc %g0, %g0, %g0;
33 #define GLOBAL_SPARE %g5
H A DNG2memcpy.S17 clr %g1; clr %g2; clr %g3; clr %g5; subcc %g0, %g0, %g0;
23 #define GLOBAL_SPARE %g5
H A Dcsum_copy.S9 #define GLOBAL_SPARE %g5
H A DNGmemcpy.S14 #define GLOBAL_SPARE %g5
H A DU3memcpy.S21 #define GLOBAL_SPARE %g5
H A DU1memcpy.S12 #define GLOBAL_SPARE g5
/linux-4.4.14/arch/sparc/prom/
H A Dcif.S19 mov %g5, %l1
24 mov %l1, %g5
35 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %o0)
/linux-4.4.14/arch/sparc/power/
H A Dhibernate_asm.S35 stx %g5, [%g3 + SC_REG_G5]
116 ldxa [%g3 + SC_REG_G5] %asi, %g5
/linux-4.4.14/arch/sparc/
H A DMakefile27 KBUILD_CFLAGS += -m32 -mcpu=v8 -pipe -mno-fpu -fcall-used-g5 -fcall-used-g7
41 KBUILD_CFLAGS += -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare
/linux-4.4.14/tools/perf/arch/sparc/util/
H A Ddwarf-regs.c18 "%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",
/linux-4.4.14/arch/x86/crypto/sha-mb/
H A Dsha1_x8_avx2.S78 # r6 = {g7 g6 g5 g4 g3 g2 g1 g0}
87 # r5 = {h5 g5 f5 e5 d5 c5 b5 a5}
107 vshufps $0x44, \r7, \r6, \t1 # t1 = {h5 h4 g5 g4 h1 h0 g1 g0}
109 vshufps $0xDD, \t1, \r2, \r7 # r7 = {h5 g5 f5 e5 h1 g1 f1 e1}
/linux-4.4.14/drivers/staging/speakup/
H A Dspeakup_dectlk.c62 { VOL, .u.n = {"[:dv g5 %d] ", 86, 60, 86, 0, 0, NULL } },
/linux-4.4.14/include/linux/
H A Dhyperv.h1010 #define VMBUS_DEVICE(g0, g1, g2, g3, g4, g5, g6, g7, \
1012 .guid = { g0, g1, g2, g3, g4, g5, g6, g7, \
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_combios.c1506 /* imac g5 isight */ radeon_get_legacy_connector_info_from_table()
1893 DRM_INFO("Connector Table: %d (imac g5 isight)\n", radeon_get_legacy_connector_info_from_table()
2044 DRM_INFO("Connector Table: %d (mac g5 9600)\n", radeon_get_legacy_connector_info_from_table()
/linux-4.4.14/drivers/media/platform/omap/
H A Domap_vout.c110 * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3
115 * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3
/linux-4.4.14/arch/arm/mach-omap2/
H A Dmux34xx.c1170 _OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),

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