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Searched refs:g1 (Results 1 - 122 of 122) sorted by relevance

/linux-4.4.14/arch/sparc/lib/
H A D	muldi3.S	28 andcc %g0, 0, %g1 29 mulscc %g1, %i3, %g1 30 mulscc %g1, %i3, %g1 31 mulscc %g1, %i3, %g1 32 mulscc %g1, %i3, %g1 33 mulscc %g1, %i3, %g1 34 mulscc %g1, %i3, %g1 35 mulscc %g1, %i3, %g1 36 mulscc %g1, %i3, %g1 37 mulscc %g1, %i3, %g1 38 mulscc %g1, %i3, %g1 39 mulscc %g1, %i3, %g1 40 mulscc %g1, %i3, %g1 41 mulscc %g1, %i3, %g1 42 mulscc %g1, %i3, %g1 43 mulscc %g1, %i3, %g1 44 mulscc %g1, %i3, %g1 45 mulscc %g1, %i3, %g1 46 mulscc %g1, %i3, %g1 47 mulscc %g1, %i3, %g1 48 mulscc %g1, %i3, %g1 49 mulscc %g1, %i3, %g1 50 mulscc %g1, %i3, %g1 51 mulscc %g1, %i3, %g1 52 mulscc %g1, %i3, %g1 53 mulscc %g1, %i3, %g1 54 mulscc %g1, %i3, %g1 55 mulscc %g1, %i3, %g1 56 mulscc %g1, %i3, %g1 57 mulscc %g1, %i3, %g1 58 mulscc %g1, %i3, %g1 59 mulscc %g1, %i3, %g1 60 mulscc %g1, %i3, %g1 61 mulscc %g1, 0, %g1 62 add %g1, %g2, %l2
H A D	NG4memset.S	18 sllx %o4, 8, %g1 19 or %g1, %o4, %o2 20 sllx %o2, 16, %g1 21 or %g1, %o2, %o2 22 sllx %o2, 32, %g1 24 or %g1, %o2, %o4 34 sub %g0, %o0, %g1 35 and %g1, 0x7, %g1 36 brz,pt %g1, .Laligned8 37 sub %o1, %g1, %o1 39 subcc %g1, 1, %g1 45 sub %g0, %o0, %g1 46 andcc %g1, (64 - 1), %g1 47 brz,pn %g1, .Laligned64 48 sub %o1, %g1, %o1 50 subcc %g1, 8, %g1 54 andn %o1, 64 - 1, %g1 55 sub %o1, %g1, %o1 59 subcc %g1, 0x40, %g1 68 andn %o1, 0x7, %g1 69 sub %o1, %g1, %o1 71 subcc %g1, 0x8, %g1 74 andcc %o1, 0x4, %g1 76 sub %o1, %g1, %o1 93 subcc %g1, 0x40, %g1
H A D	GENpatch.S	`9 sethi %hi(NEW), %g1; \ 10 or %g1, %lo(NEW), %g1; \ 13 sub %g1, %g2, %g1; \ 15 sll %g1, 11, %g1; \ 16 srl %g1, 11 + 2, %g1; \ 18 or %g3, %g1, %g3; \`
H A D	NG2patch.S	`9 sethi %hi(NEW), %g1; \ 10 or %g1, %lo(NEW), %g1; \ 13 sub %g1, %g2, %g1; \ 15 sll %g1, 11, %g1; \ 16 srl %g1, 11 + 2, %g1; \ 18 or %g3, %g1, %g3; \`
H A D	NGpatch.S	`9 sethi %hi(NEW), %g1; \ 10 or %g1, %lo(NEW), %g1; \ 13 sub %g1, %g2, %g1; \ 15 sll %g1, 11, %g1; \ 16 srl %g1, 11 + 2, %g1; \ 18 or %g3, %g1, %g3; \`
H A D	U3patch.S	`9 sethi %hi(NEW), %g1; \ 10 or %g1, %lo(NEW), %g1; \ 13 sub %g1, %g2, %g1; \ 15 sll %g1, 11, %g1; \ 16 srl %g1, 11 + 2, %g1; \ 18 or %g3, %g1, %g3; \`
H A D	udivdi3.S	33 mov 32,%g1 39 subcc %g1,1,%g1 49 subcc %g1,1,%g1 71 mov 32,%g1 77 subcc %g1,1,%g1 87 subcc %g1,1,%g1 97 mov 32,%g1 103 subcc %g1,1,%g1 113 subcc %g1,1,%g1 176 mov 32,%g1 182 subcc %g1,1,%g1 192 subcc %g1,1,%g1 205 andcc %g0,0,%g1 ! Do not move this insn 206 mulscc %g1,%o3,%g1 207 mulscc %g1,%o3,%g1 208 mulscc %g1,%o3,%g1 209 mulscc %g1,%o3,%g1 210 mulscc %g1,%o3,%g1 211 mulscc %g1,%o3,%g1 212 mulscc %g1,%o3,%g1 213 mulscc %g1,%o3,%g1 214 mulscc %g1,%o3,%g1 215 mulscc %g1,%o3,%g1 216 mulscc %g1,%o3,%g1 217 mulscc %g1,%o3,%g1 218 mulscc %g1,%o3,%g1 219 mulscc %g1,%o3,%g1 220 mulscc %g1,%o3,%g1 221 mulscc %g1,%o3,%g1 222 mulscc %g1,%o3,%g1 223 mulscc %g1,%o3,%g1 224 mulscc %g1,%o3,%g1 225 mulscc %g1,%o3,%g1 226 mulscc %g1,%o3,%g1 227 mulscc %g1,%o3,%g1 228 mulscc %g1,%o3,%g1 229 mulscc %g1,%o3,%g1 230 mulscc %g1,%o3,%g1 231 mulscc %g1,%o3,%g1 232 mulscc %g1,%o3,%g1 233 mulscc %g1,%o3,%g1 234 mulscc %g1,%o3,%g1 235 mulscc %g1,%o3,%g1 236 mulscc %g1,%o3,%g1 237 mulscc %g1,%o3,%g1 238 mulscc %g1,0,%g1 239 add %g1,%g2,%o0
H A D	GENbzero.S	23 sllx %o3, 8, %g1 24 or %g1, %o3, %o2 25 sllx %o2, 16, %g1 26 or %g1, %o2, %o2 27 sllx %o2, 32, %g1 29 or %g1, %o2, %o2 48 andcc %o0, 0x7, %g1 51 sub %g2, %g1, %g1 52 sub %o1, %g1, %o1 54 subcc %g1, 1, %g1 59 andcc %o0, (64 - 1), %g1 62 sub %g2, %g1, %g1 63 sub %o1, %g1, %o1 65 subcc %g1, 8, %g1 70 andn %o1, (64 - 1), %g1 71 sub %o1, %g1, %o1 81 subcc %g1, 64, %g1 89 andncc %o1, 0x7, %g1 91 sub %o1, %g1, %o1 93 subcc %g1, 8, %g1 132 sethi %hi(NEW), %g1; \ 133 or %g1, %lo(NEW), %g1; \ 136 sub %g1, %g2, %g1; \ 138 sll %g1, 11, %g1; \ 139 srl %g1, 11 + 2, %g1; \ 141 or %g3, %g1, %g3; \
H A D	atomic_64.S	21 1: lduw [%o1], %g1; \ 22 op %g1, %o0, %g7; \ 23 cas [%o1], %g1, %g7; \ 24 cmp %g1, %g7; \ 35 1: lduw [%o1], %g1; \ 36 op %g1, %o0, %g7; \ 37 cas [%o1], %g1, %g7; \ 38 cmp %g1, %g7; \ 40 op %g1, %o0, %g1; \ 42 sra %g1, 0, %o0; \ 61 1: ldx [%o1], %g1; \ 62 op %g1, %o0, %g7; \ 63 casx [%o1], %g1, %g7; \ 64 cmp %g1, %g7; \ 75 1: ldx [%o1], %g1; \ 76 op %g1, %o0, %g7; \ 77 casx [%o1], %g1, %g7; \ 78 cmp %g1, %g7; \ 82 op %g1, %o0, %o0; \ 100 1: ldx [%o0], %g1 101 brlez,pn %g1, 3f 102 sub %g1, 1, %g7 103 casx [%o0], %g1, %g7 104 cmp %g1, %g7 108 sub %g1, 1, %o0
H A D	locks.S	`25 ldstub [%g1 + 3], %g2 27 ldub [%g1 + 3], %g2 31 ldstub [%g1 + 3], %g2 34 ld [%g1], %g2 40 ldstub [%g1 + 3], %g2 42 ldub [%g1 + 3], %g2 46 ldstub [%g1 + 3], %g2 48 ld [%g1], %g2 54 ldub [%g1 + 3], %g2 55 ld [%g1], %g2 57 st %g2, [%g1] 65 ldub [%g1 + 3], %g2 66 ld [%g1], %g2 68 st %g2, [%g1] 76 ld [%g1], %g2 78 st %g2, [%g1] 87 ld [%g1], %g2 90 stb %g0, [%g1 + 3]`
H A D	divdi3.S	56 mov 32,%g1 62 subcc %g1,1,%g1 72 subcc %g1,1,%g1 92 mov 32,%g1 98 subcc %g1,1,%g1 108 subcc %g1,1,%g1 116 mov 32,%g1 122 subcc %g1,1,%g1 132 subcc %g1,1,%g1 191 mov 32,%g1 197 subcc %g1,1,%g1 207 subcc %g1,1,%g1 217 andcc %g0,0,%g1 ! Do not move this insn 218 mulscc %g1,%o4,%g1 219 mulscc %g1,%o4,%g1 220 mulscc %g1,%o4,%g1 221 mulscc %g1,%o4,%g1 222 mulscc %g1,%o4,%g1 223 mulscc %g1,%o4,%g1 224 mulscc %g1,%o4,%g1 225 mulscc %g1,%o4,%g1 226 mulscc %g1,%o4,%g1 227 mulscc %g1,%o4,%g1 228 mulscc %g1,%o4,%g1 229 mulscc %g1,%o4,%g1 230 mulscc %g1,%o4,%g1 231 mulscc %g1,%o4,%g1 232 mulscc %g1,%o4,%g1 233 mulscc %g1,%o4,%g1 234 mulscc %g1,%o4,%g1 235 mulscc %g1,%o4,%g1 236 mulscc %g1,%o4,%g1 237 mulscc %g1,%o4,%g1 238 mulscc %g1,%o4,%g1 239 mulscc %g1,%o4,%g1 240 mulscc %g1,%o4,%g1 241 mulscc %g1,%o4,%g1 242 mulscc %g1,%o4,%g1 243 mulscc %g1,%o4,%g1 244 mulscc %g1,%o4,%g1 245 mulscc %g1,%o4,%g1 246 mulscc %g1,%o4,%g1 247 mulscc %g1,%o4,%g1 248 mulscc %g1,%o4,%g1 249 mulscc %g1,%o4,%g1 250 mulscc %g1,0,%g1 251 add %g1,%g2,%o0
H A D	NG4patch.S	`9 sethi %hi(NEW), %g1; \ 10 or %g1, %lo(NEW), %g1; \ 13 sub %g1, %g2, %g1; \ 15 sll %g1, 11, %g1; \ 16 srl %g1, 11 + 2, %g1; \ 18 or %g3, %g1, %g3; \`
H A D	VISsave.S	`18 /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */ 26 ldub [%g6 + TI_FPDEPTH], %g1 27 brnz,a,pn %g1, 1f 28 cmp %g1, 1 35 srl %g1, 1, %g1 41 clr %g1 45 2: add %g6, %g1, %g3 47 sll %g1, 3, %g1 50 add %g6, %g1, %g3 53 add %g6, %g1, %g2 55 sll %g1, 5, %g1 64 stda %f0, [%g2 + %g1] ASI_BLK_P 65 stda %f16, [%g3 + %g1] ASI_BLK_P 69 4: add %g1, 128, %g1 71 stda %f32, [%g2 + %g1] ASI_BLK_P 73 stda %f48, [%g3 + %g1] ASI_BLK_P`
H A D	NGbzero.S	22 sllx %o3, 8, %g1 23 or %g1, %o3, %o2 24 sllx %o2, 16, %g1 25 or %g1, %o2, %o2 26 sllx %o2, 32, %g1 28 or %g1, %o2, %o2 49 andcc %o0, 0x7, %g1 52 sub %g2, %g1, %g1 53 sub %o1, %g1, %o1 55 subcc %g1, 1, %g1 60 andcc %o0, (64 - 1), %g1 63 sub %g2, %g1, %g1 64 sub %o1, %g1, %o1 66 subcc %g1, 8, %g1 72 andn %o1, (64 - 1), %g1 73 sub %o1, %g1, %o1 83 subcc %g1, 64, %g1 91 andncc %o1, 0x7, %g1 93 sub %o1, %g1, %o1 95 subcc %g1, 8, %g1 135 sethi %hi(NEW), %g1; \ 136 or %g1, %lo(NEW), %g1; \ 139 sub %g1, %g2, %g1; \ 141 sll %g1, 11, %g1; \ 142 srl %g1, 11 + 2, %g1; \ 144 or %g3, %g1, %g3; \
H A D	NG4memcpy.S	26 clr %g1; clr %g2; clr %g3; clr %g5; subcc %g0, %g0, %g0; 122 sub %g0, %o0, %g1 123 and %g1, 0x7, %g1 124 brz,pt %g1, 51f 125 sub %o2, %g1, %o2 129 subcc %g1, 1, %g1 148 sub %g0, %o0, %g1 153 and %g1, 0x3f, %g1 154 brz,pt %g1, .Llarge_aligned 155 sub %o2, %g1, %o2 159 subcc %g1, 8, %g1 169 1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1)) 176 EX_ST(STORE_INIT(%g1, %o0)) 217 alignaddr %o1, %g0, %g1 219 EX_LD_FP(LOAD(ldd, %g1 + 0x00, %f0)) 220 1: EX_LD_FP(LOAD(ldd, %g1 + 0x08, %f2)) 222 EX_LD_FP(LOAD(ldd, %g1 + 0x10, %f4)) 223 EX_LD_FP(LOAD(ldd, %g1 + 0x18, %f6)) 224 EX_LD_FP(LOAD(ldd, %g1 + 0x20, %f8)) 225 EX_LD_FP(LOAD(ldd, %g1 + 0x28, %f10)) 226 EX_LD_FP(LOAD(ldd, %g1 + 0x30, %f12)) 227 EX_LD_FP(LOAD(ldd, %g1 + 0x38, %f14)) 229 EX_LD_FP(LOAD(ldd, %g1 + 0x40, %f0)) 231 add %g1, 0x40, %g1 248 LOAD(prefetch, %g1 + 0x200, #n_reads_strong) 273 1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1)) 279 EX_ST(STORE(stx, %g1, %o0 + 0x00)) 288 1: EX_LD(LOAD(ldx, %o1 + 0x00, %g1)) 293 EX_ST(STORE(stx, %g1, %o0 - 0x08)) 298 EX_LD(LOAD(lduw, %o1 + 0x00, %g1)) 303 EX_ST(STORE(stw, %g1, %o0 - 0x04)) 307 sub %g0, %o0, %g1 308 and %g1, 0x7, %g1 309 brz,pt %g1, 2f 310 sub %o2, %g1, %o2 314 subcc %g1, 1, %g1 319 and %o1, 0x7, %g1 320 brz,pn %g1, .Lmedium_noprefetch 321 sll %g1, 3, %g1 323 sub %g2, %g1, %g2 326 sllx %o4, %g1, %o4 337 sllx %g3, %g1, %o4 338 srl %g1, 3, %g1 339 add %o1, %g1, %o1 345 EX_LD(LOAD(ldub, %o1 + 0x00, %g1)) 348 EX_ST(STORE(stb, %g1, %o0 + 0x00)) 349 EX_LD(LOAD(ldub, %o1 + 0x01, %g1)) 352 EX_ST(STORE(stb, %g1, %o0 + 0x01)) 353 EX_LD(LOAD(ldub, %o1 + 0x02, %g1)) 355 EX_ST(STORE(stb, %g1, %o0 + 0x02)) 363 EX_LD(LOAD(lduw, %o1 + 0x00, %g1)) 368 EX_ST(STORE(stw, %g1, %o0 - 0x04)) 374 1: EX_LD(LOAD(ldub, %o1 + 0x00, %g1)) 379 EX_ST(STORE(stb, %g1, %o0 - 0x01))
H A D	GENpage.S	`53 sethi %hi(NEW), %g1; \ 54 or %g1, %lo(NEW), %g1; \ 57 sub %g1, %g2, %g1; \ 59 sll %g1, 11, %g1; \ 60 srl %g1, 11 + 2, %g1; \ 62 or %g3, %g1, %g3; \`
H A D	mcount.S	`27 sethi %hi(ftrace_trace_function), %g1 29 ldx [%g1 + %lo(ftrace_trace_function)], %g1 31 cmp %g1, %g2 36 jmpl %g1, %o7 43 sethi %hi(ftrace_graph_return), %g1 44 ldx [%g1 + %lo(ftrace_graph_return)], %g3 48 sethi %hi(ftrace_graph_entry), %g1 50 ldx [%g1 + %lo(ftrace_graph_entry)], %g1 51 cmp %g1, %g2`
H A D	GENcopy_from_user.S	`24 rd %asi, %g1; \ 25 cmp %g1, ASI_AIUS; \`
H A D	GENmemcpy.S	`76 EX_LD(LOAD(ldub, %o1, %g1)) 77 EX_ST(STORE(stb, %g1, %o0)) 82 andn %o2, 0x7, %g1 83 sub %o2, %g1, %o2 84 1: subcc %g1, 0x8, %g1 103 EX_LD(LOAD(lduw, %o1, %g1)) 104 EX_ST(STORE(stw, %g1, %o1 + %o3)) 114 EX_LD(LOAD(ldub, %o1, %g1)) 115 EX_ST(STORE(stb, %g1, %o1 + %o3))`
H A D	csum_copy.S	68 xor %o0, %o1, %g1 70 andcc %g1, 0x3, %g0 103 EX_LD(LOAD(lduw, %o0 + 0x04, %g1)) 108 add %o4, %g1, %o4 109 EX_ST(STORE(stw, %g1, %o1 + 0x04)) 110 EX_LD(LOAD(lduw, %o0 + 0x10, %g1)) 117 add %o4, %g1, %o4 118 EX_ST(STORE(stw, %g1, %o1 + 0x10)) 119 EX_LD(LOAD(lduw, %o0 + 0x1c, %g1)) 126 add %o4, %g1, %o4 127 EX_ST(STORE(stw, %g1, %o1 + 0x1c)) 128 EX_LD(LOAD(lduw, %o0 + 0x28, %g1)) 135 add %o4, %g1, %o4 136 EX_ST(STORE(stw, %g1, %o1 + 0x28)) 137 EX_LD(LOAD(lduw, %o0 + 0x34, %g1)) 144 add %o4, %g1, %o4 145 EX_ST(STORE(stw, %g1, %o1 + 0x34)) 177 sethi %hi(0xffff0000), %g1 179 andn %o4, %g1, %g2 182 andn %o4, %g1, %g2 207 sethi %hi(0xffff0000), %g1 209 andn %o4, %g1, %g2 212 andn %o4, %g1, %g2 220 and %o4, 0xff, %g1 221 sll %g1, 8, %g1 222 or %o5, %g1, %o4 235 srl %o2, 1, %g1 240 srl %o2, 1, %g1 242 1: brz,a,pn %g1, 3f 246 srl %g1, 1, %g1 250 sub %g1, 1, %g1 255 srl %g1, 1, %g1 257 1: brz,a,pn %g1, 2f 271 subcc %g1, 1, %g1
H A D	checksum_64.S	`70 lduw [%o0 + 0x04], %g1 74 add %o4, %g1, %o4 77 lduw [%o0 + 0x14], %g1 82 add %o4, %g1, %o4 85 lduw [%o0 + 0x24], %g1 90 add %o4, %g1, %o4 93 lduw [%o0 + 0x34], %g1 98 add %o4, %g1, %o4 125 sethi %hi(0xffff0000), %g1 127 andn %o4, %g1, %g2 130 andn %o4, %g1, %g2 151 sethi %hi(0xffff0000), %g1 153 andn %o4, %g1, %g2 156 andn %o4, %g1, %g2 164 and %o4, 0xff, %g1 165 sll %g1, 8, %g1 166 or %o5, %g1, %o4`
H A D	NG2memcpy.S	17 clr %g1; clr %g2; clr %g3; clr %g5; subcc %g0, %g0, %g0; 233 EX_LD(LOAD(ldub, %o1, %g1)) 234 EX_ST(STORE(stb, %g1, %o0)) 240 /* Clobbers o5/g1/g2/g3/g7/icc/xcc. We must preserve 250 andn %o2, (64 - 1), %g1 251 sub %o2, %g1, %o2 254 add %o1, %g1, %o1 290 subcc %g1, 64, %g1 304 subcc %g1, 64, %g1 318 subcc %g1, 64, %g1 332 subcc %g1, 64, %g1 346 subcc %g1, 64, %g1 360 subcc %g1, 64, %g1 374 subcc %g1, 64, %g1 388 subcc %g1, 64, %g1 397 subcc %g1, 64, %g1 428 EX_LD(LOAD(ldx, %o1, %g1)) 432 EX_ST(STORE(stx, %g1, %o1 + GLOBAL_SPARE)) 456 andcc %o0, 0x7, %g1 457 sub %g1, 0x8, %g1 459 sub %g0, %g1, %g1 460 sub %o2, %g1, %o2 462 1: subcc %g1, 1, %g1 469 andcc %o1, 0x7, %g1 471 sll %g1, 3, %g1 481 sub GLOBAL_SPARE, %g1, GLOBAL_SPARE 483 sllx %g2, %g1, %g2 492 sllx %g3, %g1, %g2 494 srl %g1, 3, %g1 497 add %o1, %g1, %o1 509 EX_LD(LOAD(lduw, %o1, %g1)) 510 EX_ST(STORE(stw, %g1, %o1 + GLOBAL_SPARE)) 520 EX_LD(LOAD(ldub, %o1, %g1)) 521 EX_ST(STORE(stb, %g1, %o1 + GLOBAL_SPARE))
H A D	GENcopy_to_user.S	`28 rd %asi, %g1; \ 29 cmp %g1, ASI_AIUS; \`
H A D	NG2copy_from_user.S	`37 rd %asi, %g1; \ 38 cmp %g1, ASI_AIUS; \`
H A D	NG4copy_from_user.S	`32 rd %asi, %g1; \ 33 cmp %g1, ASI_AIUS; \`
H A D	NGcopy_from_user.S	`26 rd %asi, %g1; \ 27 cmp %g1, ASI_AIUS; \`
H A D	NGcopy_to_user.S	`29 rd %asi, %g1; \ 30 cmp %g1, ASI_AIUS; \`
H A D	clear_page.S	`47 sub %o0, %g2, %g1 ! paddr 51 or %g1, %g3, %g1 ! TTE data 65 stxa %g1, [%g0] ASI_DTLB_DATA_IN 66 sethi %hi(KERNBASE), %g1 67 flush %g1 77 mov %o0, %g1 ! remember vaddr for tlbflush 97 stxa %g0, [%g1] ASI_DMMU_DEMAP`
H A D	bzero.S	`14 sllx %o3, 8, %g1 15 or %g1, %o3, %o2 16 sllx %o2, 16, %g1 17 or %g1, %o2, %o2 18 sllx %o2, 32, %g1 20 or %g1, %o2, %o2 41 3: and %o1, 0x38, %g1 63 brz,pn %g1, 6f 66 subcc %g1, 8, %g1 107 3: and %o1, 0x38, %g1 129 brz,pn %g1, 6f 132 subcc %g1, 8, %g1`
H A D	copy_user.S	164 mov %o2, %g1 167 sub %g1, 4, %g1 172 andcc %g1, 0xffffff80, %g7 189 andcc %g1, 0x70, %g7 191 andcc %g1, 8, %g0 212 andcc %g1, 4, %g0 214 EX(ldd [%o1], %g2, and %g1, 0xf) 217 EX(st %g2, [%o0 - 0x08], and %g1, 0xf) 218 EX2(st %g3, [%o0 - 0x04], and %g1, 0xf, %g1, sub %g1, 4) 221 andcc %g1, 2, %g0 223 EX(ld [%o1], %g2, and %g1, 7) 225 EX(st %g2, [%o0], and %g1, 7) 229 andcc %g1, 1, %g0 231 EX(lduh [%o1], %g2, and %g1, 3) 233 EX(sth %g2, [%o0], and %g1, 3) 257 andcc %g1, 0x70, %g7 259 andcc %g1, 8, %g0 358 mov %o2, %g1 365 sethi %hi(PAGE_OFFSET), %g1 366 cmp %o0, %g1 368 cmp %o1, %g1 370 ld [%g6 + TI_PREEMPT], %g1 371 cmp %g1, 0 387 * g3 = g1 + g7 - ((g2 / 12) * 32 + (x < 4) ? 0 : (x - 4) * 4); 409 60: and %g1, 0x7f, %g3 416 * g3 = (g1 & 15) + (i / 6) * 16 + (j < 4) ? (j + 1) * 4 : 16; 420 and %g1, 0xf, %g1 422 add %o0, %g1, %o0 426 add %g1, 16, %g1 433 2: add %g1, %g2, %g3 437 /* g3 = g1 + g7 - (g2 / 8) * 32 + (g2 & 4) ? (g2 & 3) * 8 : 0;
H A D	checksum_32.S	113 andcc %o1, 0x70, %g1 ! clears carry flag too 122 andcc %o1, 0x70, %g1 ! clears carry flag too 125 srl %g1, 1, %o4 ! compute offset 126 sub %g7, %g1, %g7 ! adjust jmp ptr 129 add %o0, %g1, %o0 ! advance buf ptr 292 cmp %g1, 16 294 srl %g1, 1, %o3 297 andcc %g1, 0xf, %o3 306 EX(lduh [%o0 + 0x00], %g4, add %g1, 0) 307 sub %g1, 2, %g1 321 andcc %g1, 0xffffff80, %g0 322 EX(ld [%o0 + 0x00], %g4, add %g1, 0) 323 sub %g1, 4, %g1 330 andcc %g1, 0xffffff80, %g0 339 /* %o0=src, %o1=dest, %g1=len, %g7=sum / 345 andcc %g1, 0xffffff80, %g0 ! can we use unrolled loop? 354 sub %g1, 128, %g1 ! detract from length 356 andcc %g1, 0xffffff80, %g0 ! more to csum? 360 3: andcc %g1, 0x70, %o2 ! can use table? 362 andcc %g1, 0xf, %o3 ! get low bits of length (clears carry btw) 390 sub %g1, 128, %g1 ! detract from length 392 andcc %g1, 0xffffff80, %g0 ! more to csum? 397 andcc %g1, 0x70, %o2 ! can use table? (clears carry btw) 399 ccslow: cmp %g1, 0 404 srl %g1, 1, %g4 405 sub %g1, 1, %g1 406 EX(ldub [%o0], %g5, add %g1, 1) 409 srl %g1, 1, %g4 413 andcc %g1, 1, %g0 417 EX(lduh [%o0], %o4, add %g1, 0) 418 sub %g1, 2, %g1 429 andcc %g1, 2, %g0 448 andcc %g1, 2, %g0 451 andcc %g1, 1, %g0 452 EX(lduh [%o0], %o4, and %g1, 3) 453 andcc %g1, 1, %g0 486 o3 = g1 - (g2/20)32 - o2 / 491 sub %g1, 32, %g1 497 sub %g1, %o2, %o3 500 * o3 = g1 - (g2/16)32 - o2 / 511 sub %g1, %g2, %o3 539 and %g1, 3, %g1 541 add %g1, %g4, %o3
H A D	NGmemcpy.S	129 EX_LD(LOAD(ldub, %i1, %g1)) 130 EX_ST(STORE(stb, %g1, %o0)) 151 andn %i2, (64 - 1), %g1 ! block copy loop iterator 153 sub %i2, %g1, %i2 ! final sub-block copy bytes 207 subcc %g1, 64, %g1 240 subcc %g1, 64, %g1 271 subcc %g1, 64, %g1 299 subcc %g1, 64, %g1 326 EX_LD(LOAD(ldx, %i1, %g1)) 330 EX_ST(STORE(stx, %g1, %i1 + %i3)) 354 andcc %o0, 0x7, %g1 355 sub %g1, 0x8, %g1 357 sub %g0, %g1, %g1 358 sub %i2, %g1, %i2 360 1: subcc %g1, 1, %g1 367 andcc %i1, 0x7, %g1 369 sll %g1, 3, %g1 379 sub %i3, %g1, %i3 381 sllx %g2, %g1, %g2 390 sllx %g3, %g1, %g2 392 srl %g1, 3, %g1 395 add %i1, %g1, %i1 407 EX_LD(LOAD(lduw, %i1, %g1)) 408 EX_ST(STORE(stw, %g1, %i1 + %i3)) 418 EX_LD(LOAD(ldub, %i1, %g1)) 419 EX_ST(STORE(stb, %g1, %i1 + %i3))
H A D	U3memcpy.S	15 clr %g1; clr %g2; clr %g3; subcc %g0, %g0, %g0; 107 /* Clobbers o5/g1/g2/g3/g7/icc/xcc. We must preserve 124 andcc %g2, 0x7, %g1 128 1: subcc %g1, 0x1, %g1 137 and %o1, 0x7, %g1 235 cmp %g1, 0 258 cmp %g1, 0 280 * Note that %g1 is (src & 0x3) saved above before the 285 add %o1, %g1, %o1 290 andcc %g1, 0x7, %g0 330 EX_LD(LOAD(ldx, %o1 + 0x08, %g1)) 333 EX_ST(STORE(stx, %g1, %o1 + %o3)) 357 andcc %o0, 0x7, %g1 358 sub %g1, 0x8, %g1 360 sub %g0, %g1, %g1 361 sub %o2, %g1, %o2 363 1: subcc %g1, 1, %g1 370 andcc %o1, 0x7, %g1 372 sll %g1, 3, %g1 382 sub %o3, %g1, %o3 384 sllx %g2, %g1, %g2 393 sllx %g3, %g1, %g2 395 srl %g1, 3, %g1 398 add %o1, %g1, %o1 410 EX_LD(LOAD(lduw, %o1, %g1)) 411 EX_ST(STORE(stw, %g1, %o1 + %o3)) 421 EX_LD(LOAD(ldub, %o1, %g1)) 422 EX_ST(STORE(stb, %g1, %o1 + %o3))
H A D	NG2copy_to_user.S	`46 rd %asi, %g1; \ 47 cmp %g1, ASI_AIUS; \`
H A D	NG4copy_to_user.S	`41 rd %asi, %g1; \ 42 cmp %g1, ASI_AIUS; \`
H A D	U1copy_from_user.S	`32 rd %asi, %g1; \ 33 cmp %g1, ASI_AIUS; \`
H A D	U1copy_to_user.S	`32 rd %asi, %g1; \ 33 cmp %g1, ASI_AIUS; \`
H A D	U3copy_to_user.S	`32 rd %asi, %g1; \ 33 cmp %g1, ASI_AIUS; \`
H A D	copy_in_user.S	`73 EX(lduwa [%o1] %asi, %g1) 74 EX(stwa %g1, [%o0] %asi) 85 EX(lduba [%o1] %asi, %g1) 86 EX(stba %g1, [%o0] %asi)`
H A D	NGpage.S	`113 sethi %hi(NEW), %g1; \ 114 or %g1, %lo(NEW), %g1; \ 117 sub %g1, %g2, %g1; \ 119 sll %g1, 11, %g1; \ 120 srl %g1, 11 + 2, %g1; \ 122 or %g3, %g1, %g3; \`
H A D	memcpy.S	222 mov %o2, %g1 225 sub %g1, 4, %g1 230 andcc %g1, 0xffffff80, %g0 240 sub %g1, 128, %g1 242 cmp %g1, 128 246 andcc %g1, 0x70, %g4 248 andcc %g1, 8, %g0 270 andcc %g1, 4, %g0 281 andcc %g1, 2, %g0 289 andcc %g1, 1, %g0 310 subcc %g1, 128, %g1 312 cmp %g1, 128 316 andcc %g1, 0x70, %g4 318 andcc %g1, 8, %g0 338 andcc %g1, 4, %g0 346 andcc %g1, 2, %g0 354 andcc %g1, 1, %g0 425 ld [%i1], %g1 434 ld [%i1 + 4], %g1 443 srl %g1, %l0, %g5 448 sll %g1, %g4, %g2 459 ld [%i1 + 12], %g1 471 srl %g1, %l0, %g5 541 mov %o2, %g1
H A D	U1memcpy.S	17 clr %g1; clr %g2; clr %g3; subcc %g0, %g0, %g0; 149 /* Clobbers o5/g1/g2/g3/g7/icc/xcc. */ 164 andcc %g2, 0x7, %g1 168 1: subcc %g1, 0x1, %g1 177 and %o1, 0x7, %g1 203 add %o1, %g1, %g1 205 srl %g1, 3, %g2 214 add %g1, %GLOBAL_SPARE, %g1 219 add %g1, %g3, %g1 451 mov %g1, %o1 473 EX_LD(LOAD(ldx, %o1 + 0x08, %g1)) 477 EX_ST(STORE(stx, %g1, %o1 + %o3)) 500 75: andcc %o0, 0x7, %g1 501 sub %g1, 0x8, %g1 503 sub %g0, %g1, %g1 504 sub %o2, %g1, %o2 507 subcc %g1, 1, %g1 513 andcc %o1, 0x7, %g1 515 sll %g1, 3, %g1 525 sub %o3, %g1, %o3 527 sllx %g2, %g1, %g2 536 sllx %g3, %g1, %g2 538 srl %g1, 3, %g1 541 add %o1, %g1, %o1 551 1: EX_LD(LOAD(lduw, %o1, %g1)) 553 EX_ST(STORE(stw, %g1, %o1 + %o3)) 561 90: EX_LD(LOAD(ldub, %o1, %g1)) 563 EX_ST(STORE(stb, %g1, %o1 + %o3))
H A D	blockops.S	`11 * Assumes %g1 contains zero. 52 or %g0, %g0, %g1 72 or %g0, (PAGE_SIZE >> 8), %g1 82 subcc %g1, 1, %g1`
H A D	NG4copy_page.S	`32 ldx [%o1 + 0x20], %g1 45 stxa %g1, [%o0] ASI_ST_BLKINIT_MRU_P`
H A D	copy_page.S	`56 sub %o0, %g2, %g1 ! dest paddr 61 or %g1, %g3, %g1 ! dest TTE data 80 stxa %g1, [%g0] ASI_DTLB_DATA_IN 95 mov %o0, %g1 170 mov %o0, %g1 229 stxa %g0, [%g1] ASI_DMMU_DEMAP 233 stxa %g0, [%g1 + %g2] ASI_DMMU_DEMAP`
H A D	memset.S	`69 mov %o0, %g1 175 mov %g1, %o0`
/linux-4.4.14/arch/sparc/math-emu/
H A D	sfp-util_32.h	32 "andcc %%g0,0,%%g1 ! Don't move this insn\n\t" \ 33 "mulscc %%g1,%3,%%g1\n\t" \ 34 "mulscc %%g1,%3,%%g1\n\t" \ 35 "mulscc %%g1,%3,%%g1\n\t" \ 36 "mulscc %%g1,%3,%%g1\n\t" \ 37 "mulscc %%g1,%3,%%g1\n\t" \ 38 "mulscc %%g1,%3,%%g1\n\t" \ 39 "mulscc %%g1,%3,%%g1\n\t" \ 40 "mulscc %%g1,%3,%%g1\n\t" \ 41 "mulscc %%g1,%3,%%g1\n\t" \ 42 "mulscc %%g1,%3,%%g1\n\t" \ 43 "mulscc %%g1,%3,%%g1\n\t" \ 44 "mulscc %%g1,%3,%%g1\n\t" \ 45 "mulscc %%g1,%3,%%g1\n\t" \ 46 "mulscc %%g1,%3,%%g1\n\t" \ 47 "mulscc %%g1,%3,%%g1\n\t" \ 48 "mulscc %%g1,%3,%%g1\n\t" \ 49 "mulscc %%g1,%3,%%g1\n\t" \ 50 "mulscc %%g1,%3,%%g1\n\t" \ 51 "mulscc %%g1,%3,%%g1\n\t" \ 52 "mulscc %%g1,%3,%%g1\n\t" \ 53 "mulscc %%g1,%3,%%g1\n\t" \ 54 "mulscc %%g1,%3,%%g1\n\t" \ 55 "mulscc %%g1,%3,%%g1\n\t" \ 56 "mulscc %%g1,%3,%%g1\n\t" \ 57 "mulscc %%g1,%3,%%g1\n\t" \ 58 "mulscc %%g1,%3,%%g1\n\t" \ 59 "mulscc %%g1,%3,%%g1\n\t" \ 60 "mulscc %%g1,%3,%%g1\n\t" \ 61 "mulscc %%g1,%3,%%g1\n\t" \ 62 "mulscc %%g1,%3,%%g1\n\t" \ 63 "mulscc %%g1,%3,%%g1\n\t" \ 64 "mulscc %%g1,%3,%%g1\n\t" \ 65 "mulscc %%g1,0,%%g1\n\t" \ 66 "add %%g1,%%g2,%0\n\t" \ 72 : "%g1", "%g2", "cc") 78 "mov 32,%%g1\n\t" \ 84 "subcc %%g1,1,%%g1\n\t" \ 94 "subcc %%g1,1,%%g1\n\t" \ 105 "0" ((USItype)(n0)) : "%g1", "cc")
/linux-4.4.14/arch/sparc/kernel/
H A D	una_asm_32.S	26 ld [%o2], %g1 31 srl %g1, 24, %g2 32 srl %g1, 16, %g7 34 srl %g1, 8, %g2 39 7: stb %g1, [%o0 + 3] 40 srl %g7, 16, %g1 43 9: stb %g1, [%o0 + 5] 47 1: srl %g1, 16, %g7 49 srl %g1, 8, %g2 53 15: stb %g1, [%o0 + 3] 54 2: srl %g1, 8, %g2 56 17: stb %g1, [%o0 + 1] 93 4: ldub [%o2], %g1 95 sll %g1, 8, %g1 98 or %g1, %g2, %g1 99 sll %g1, 16, %g1 100 sra %g1, 16, %g1 102 st %g1, [%o0] 104 sll %g1, 24, %g1 111 or %g1, %g7, %g1 113 st %g1, [%o0] 114 9: ldub [%o2], %g1 116 sll %g1, 24, %g1 121 or %g1, %g2, %g1 123 or %g1, %g7, %g7 124 13: ldub [%o2 + 4], %g1 127 sll %g1, 24, %g1 132 or %g1, %g2, %g1 134 or %g1, %g7, %g7
H A D	utrap.S	`4 TRAP_LOAD_THREAD_REG(%g6, %g1) 5 ldx [%g6 + TI_UTRAPS], %g1 6 brnz,pt %g1, invoke_utrap 18 ldx [%g1 + %g3], %g1 26 wrpr %g1, 0, %tnpc`
H A D	urtt_fill.S	`11 rdpr %cwp, %g1 12 add %g1, 1, %g1 13 wrpr %g1, 0x0, %cwp 23 mov PRIMARY_CONTEXT, %g1 25 661: stxa %g2, [%g1] ASI_DMMU 28 stxa %g2, [%g1] ASI_MMU 31 sethi %hi(KERNBASE), %g1 32 flush %g1 56 LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3) 70 sethi %hi(tlb_type), %g1 71 lduw [%g1 + %lo(tlb_type)], %g1 72 cmp %g1, 3 85 2: sethi %hi(tlb_type), %g1 87 lduw [%g1 + %lo(tlb_type)], %g1 89 cmp %g1, 3`
H A D	winfixup.S	24 TRAP_LOAD_THREAD_REG(%g6, %g1) 25 rdpr %tstate, %g1 26 and %g1, TSTATE_CWP, %g1 30 wrpr %g1, %cwp 43 TRAP_LOAD_THREAD_REG(%g6, %g1) 44 ldx [%g6 + TI_FLAGS], %g1 46 movne %icc, 0, %g1 47 andcc %g1, _TIF_32BIT, %g0 48 ldub [%g6 + TI_WSAVED], %g1 49 sll %g1, 3, %g3 52 sll %g1, 7, %g3 88 2: add %g1, 1, %g1 89 stb %g1, [%g6 + TI_WSAVED] 90 rdpr %tstate, %g1 91 andcc %g1, TSTATE_PRIV, %g0 94 and %g1, TSTATE_CWP, %g1 99 wrpr %g1, %cwp 113 rdpr %tstate, %g1 114 and %g1, TSTATE_CWP, %g1 115 wrpr %g1, %cwp 118 sethi %hi(tlb_type), %g1 119 lduw [%g1 + %lo(tlb_type)], %g1 120 cmp %g1, 3 140 rdpr %tstate, %g1 141 and %g1, TSTATE_CWP, %g1 142 wrpr %g1, %cwp 145 sethi %hi(tlb_type), %g1 147 lduw [%g1 + %lo(tlb_type)], %g1 149 cmp %g1, 3
H A D	trampoline_32.S	45 set (PSR_PIL \| PSR_S \| PSR_PS), %g1 46 wr %g1, 0x0, %psr ! traps off though 50 mov 2, %g1 51 wr %g1, 0x0, %wim 69 rd %psr, %g1 70 wr %g1, PSR_ET, %psr ! traps on 99 set (PSR_PIL \| PSR_S \| PSR_PS), %g1 100 wr %g1, 0x0, %psr ! traps off though 104 mov 2, %g1 105 wr %g1, 0x0, %wim 109 set trapbase, %g1 110 wr %g1, 0x0, %tbr 117 srl %g3, 3, %g1 118 sta %g1, [%g0] ASI_M_VIKING_TMP1 130 rd %psr, %g1 131 wr %g1, PSR_ET, %psr ! traps on 151 set smp_penguin_ctable,%g1 152 ld [%g1+4],%g1 153 srl %g1,4,%g1 155 sta %g1, [%g5] ASI_LEON_MMUREGS 158 set (PSR_PIL \| PSR_S \| PSR_PS), %g1 159 wr %g1, 0x0, %psr ! traps off though 163 mov 2, %g1 164 wr %g1, 0x0, %wim 168 set trapbase, %g1 169 wr %g1, 0x0, %tbr 186 rd %psr, %g1 187 wr %g1, PSR_ET, %psr ! traps on
H A D	cherrs.S	8 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 9 andn %g1, DCU_DC \| DCU_IC, %g1 10 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 14 mov 0, %g1 21 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 22 andn %g1, DCU_DC \| DCU_IC, %g1 23 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 27 mov 1, %g1 34 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 35 andn %g1, DCU_IC, %g1 36 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 40 mov 0, %g1 47 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 48 andn %g1, DCU_IC, %g1 49 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 53 mov 1, %g1 60 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; 61 andn %g1, DCU_DC \| DCU_IC, %g1; 62 stxa %g1, [%g0] ASI_DCU_CONTROL_REG; 66 mov 0, %g1 73 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1; 74 andn %g1, DCU_DC \| DCU_IC, %g1; 75 stxa %g1, [%g0] ASI_DCU_CONTROL_REG; 79 mov 1, %g1 181 rdpr %tl, %g1 ! Save original trap level 188 wrpr %g1, %tl ! Restore original trap level 190 cmp %g2, %g1 ! Hit them all yet? 193 wrpr %g1, %tl ! Restore original trap level 196 lduw [%g2 + %lo(dcache_parity_tl1_occurred)], %g1 197 add %g1, 1, %g1 198 stw %g1, [%g2 + %lo(dcache_parity_tl1_occurred)] 200 sethi %hi(1 << 16), %g1 ! D-cache size 202 sub %g1, %g2, %g1 ! Move down 1 cacheline 203 1: srl %g1, 14, %g3 ! Compute UTAG 205 stxa %g3, [%g1] ASI_DCACHE_UTAG 209 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA 214 subcc %g1, %g2, %g1 ! Next cacheline 232 rdpr %tl, %g1 ! Save original trap level 239 wrpr %g1, %tl ! Restore original trap level 241 cmp %g2, %g1 ! Hit them all yet? 244 wrpr %g1, %tl ! Restore original trap level 247 lduw [%g2 + %lo(icache_parity_tl1_occurred)], %g1 248 add %g1, 1, %g1 249 stw %g1, [%g2 + %lo(icache_parity_tl1_occurred)] 251 sethi %hi(1 << 15), %g1 ! I-cache size 253 sub %g1, %g2, %g1 254 1: or %g1, (2 << 3), %g3 257 subcc %g1, %g2, %g1 277 sethi %hi(1 << 16), %g1 ! D-cache size 279 sub %g1, %g2, %g1 280 1: stxa %g0, [%g1] ASI_DCACHE_TAG 282 subcc %g1, %g2, %g1 285 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1 286 or %g1, (DCU_DC \| DCU_IC), %g1 287 stxa %g1, [%g0] ASI_DCU_CONTROL_REG 294 * %g1: (TL>=0) ? 1 : 0 305 and %g1, 0x1, %g1 306 sllx %g1, 63, %g2 327 sllx %g1, 8, %g1 328 add %g3, %g1, %g1 330 /* %g1 holds pointer to the top of the logging scoreboard / 331 ldx [%g1 + 0x0], %g7 336 stx %g4, [%g1 + 0x0] 337 stx %g5, [%g1 + 0x8] 338 add %g1, 0x10, %g1 340 / %g1 now points to D-cache logging area / 352 stx %g2, [%g1 + 0x20] 353 stx %g7, [%g1 + 0x28] 359 stx %g7, [%g1 + 0x30] 361 stx %g7, [%g1 + 0x38] 365 stx %g7, [%g1] 369 add %g1, 0x8, %g1 372 add %g1, 0x20, %g1 381 add %g1, 0x40, %g1 383 / %g1 now points to I-cache logging area / 397 stx %g2, [%g1 + 0x40] 398 stx %g7, [%g1 + 0x48] 402 stx %g7, [%g1 + 0x50] 405 stx %g7, [%g1 + 0x60] 407 stx %g7, [%g1 + 0x68] 410 stx %g7, [%g1 + 0x58] 415 stx %g7, [%g1] 419 add %g1, 0x8, %g1 422 add %g1, 0x30, %g1 431 add %g1, 0x70, %g1 433 / %g1 now points to E-cache logging area / 435 stx %g2, [%g1 + 0x20] 437 stx %g7, [%g1 + 0x28] 442 stx %g7, [%g1 + %g3] 466 %g1 is one if this trap occurred at %tl >= 1.
H A D	sun4v_tlb_miss.S	50 /* Load UTSB reg into %g1. / 51 mov SCRATCHPAD_UTSBREG1, %g1 52 ldxa [%g1] ASI_SCRATCHPAD, %g1 56 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7) 59 ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2 75 mov %o0, %g1 ! save %o0 86 mov %g1, %o0 ! restore %o0 96 / Load UTSB reg into %g1. */ 97 mov SCRATCHPAD_UTSBREG1, %g1 98 ldxa [%g1] ASI_SCRATCHPAD, %g1 102 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7) 105 ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2 118 mov %o0, %g1 ! save %o0 129 mov %g1, %o0 ! restore %o0 142 rdpr %tl, %g1 143 cmp %g1, 1 155 mov SCRATCHPAD_UTSBREG1, %g1 156 ldxa [%g1] ASI_SCRATCHPAD, %g1 167 mov SCRATCHPAD_UTSBREG1, %g1 168 ldxa [%g1] ASI_SCRATCHPAD, %g1 175 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7) 198 rdpr %tl, %g1 199 cmp %g1, 1 201 or %g0, FAULT_CODE_BAD_RA \| FAULT_CODE_ITLB, %g1 203 sethi %hi(sun4v_err_itlb_vaddr), %g1 204 stx %g4, [%g1 + %lo(sun4v_err_itlb_vaddr)] 205 sethi %hi(sun4v_err_itlb_ctx), %g1 208 stx %o1, [%g1 + %lo(sun4v_err_itlb_ctx)] 209 sethi %hi(sun4v_err_itlb_pte), %g1 210 stx %g3, [%g1 + %lo(sun4v_err_itlb_pte)] 211 sethi %hi(sun4v_err_itlb_error), %g1 212 stx %o0, [%g1 + %lo(sun4v_err_itlb_error)] 225 rdpr %tl, %g1 226 cmp %g1, 1 228 or %g0, FAULT_CODE_BAD_RA \| FAULT_CODE_DTLB, %g1 230 sethi %hi(sun4v_err_dtlb_vaddr), %g1 231 stx %g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)] 232 sethi %hi(sun4v_err_dtlb_ctx), %g1 235 stx %o1, [%g1 + %lo(sun4v_err_dtlb_ctx)] 236 sethi %hi(sun4v_err_dtlb_pte), %g1 237 stx %g3, [%g1 + %lo(sun4v_err_dtlb_pte)] 238 sethi %hi(sun4v_err_dtlb_error), %g1 239 stx %o0, [%g1 + %lo(sun4v_err_dtlb_error)] 254 or %g1, %g0, %g4 399 sethi %hi(NEW), %g1; \ 400 or %g1, %lo(NEW), %g1; \ 403 sub %g1, %g2, %g1; \ 405 sll %g1, 11, %g1; \ 406 srl %g1, 11 + 2, %g1; \ 408 or %g3, %g1, %g3; \
H A D	sys32.S	18 STUB: sethi %hi(SYSCALL), %g1; \ 19 jmpl %g1 + %lo(SYSCALL), %g0; \ 25 STUB: sethi %hi(SYSCALL), %g1; \ 27 jmpl %g1 + %lo(SYSCALL), %g0; \ 34 sethi %hi(SYSCALL), %g1; \ 36 jmpl %g1 + %lo(SYSCALL), %g0; \ 55 sethi %hi(sys_mmap), %g1 56 jmpl %g1 + %lo(sys_mmap), %g0 82 sethi %hi(sys_socket), %g1 84 jmpl %g1 + %lo(sys_socket), %g0 91 sethi %hi(sys_bind), %g1 93 jmpl %g1 + %lo(sys_bind), %g0 100 sethi %hi(sys_connect), %g1 102 jmpl %g1 + %lo(sys_connect), %g0 109 sethi %hi(sys_listen), %g1 110 jmpl %g1 + %lo(sys_listen), %g0 118 sethi %hi(sys_accept), %g1 120 jmpl %g1 + %lo(sys_accept), %g0 127 sethi %hi(sys_getsockname), %g1 129 jmpl %g1 + %lo(sys_getsockname), %g0 136 sethi %hi(sys_getpeername), %g1 138 jmpl %g1 + %lo(sys_getpeername), %g0 145 sethi %hi(sys_socketpair), %g1 148 jmpl %g1 + %lo(sys_socketpair), %g0 154 sethi %hi(sys_send), %g1 157 jmpl %g1 + %lo(sys_send), %g0 163 sethi %hi(sys_recv), %g1 166 jmpl %g1 + %lo(sys_recv), %g0 172 sethi %hi(sys_sendto), %g1 177 jmpl %g1 + %lo(sys_sendto), %g0 181 sethi %hi(sys_recvfrom), %g1 186 jmpl %g1 + %lo(sys_recvfrom), %g0 190 sethi %hi(sys_shutdown), %g1 191 jmpl %g1 + %lo(sys_shutdown), %g0 199 sethi %hi(compat_sys_setsockopt), %g1 203 jmpl %g1 + %lo(compat_sys_setsockopt), %g0 208 sethi %hi(compat_sys_getsockopt), %g1 212 jmpl %g1 + %lo(compat_sys_getsockopt), %g0 217 sethi %hi(compat_sys_sendmsg), %g1 219 jmpl %g1 + %lo(compat_sys_sendmsg), %g0 226 sethi %hi(compat_sys_recvmsg), %g1 228 jmpl %g1 + %lo(compat_sys_recvmsg), %g0 235 sethi %hi(sys_accept4), %g1 238 jmpl %g1 + %lo(sys_accept4), %g0
H A D	rtrap_32.S	30 rtrap_7win_patch3: srl %g1, 7, %g2 32 rtrap_7win_patch5: and %g1, 0x7f, %g1 53 sethi %hi(PSR_SYSCALL), %g1 55 andn %t_psr, %g1, %t_psr 85 sethi %hi(PSR_SYSCALL), %g1 86 andn %t_psr, %g1, %t_psr 150 LOAD_PT_YREG(sp, g1) 177 mov 2, %g1 178 sll %g1, %t_psr, %g1 179 rtrap_patch3: srl %g1, 8, %g2 180 or %g1, %g2, %g1 182 andcc %g2, %g1, %g0 184 sll %g2, 0x1, %g1 188 or %g1, %g2, %g1 189 rtrap_patch5: and %g1, 0xff, %g1 191 wr %g1, 0x0, %wim 194 LOAD_PT_ALL(sp, t_psr, t_pc, t_npc, g1) 205 LOAD_PT_ALL(sp, t_psr, t_pc, t_npc, g1) 230 sethi %hi(PAGE_OFFSET), %g1 231 cmp %g1, %fp 233 mov AC_M_SFSR, %g1 234 LEON_PI(lda [%g1] ASI_LEON_MMUREGS, %g0) 235 SUN_PI_(lda [%g1] ASI_M_MMUREGS, %g0) 237 LEON_PI(lda [%g0] ASI_LEON_MMUREGS, %g1) 238 SUN_PI_(lda [%g0] ASI_M_MMUREGS, %g1) 239 or %g1, 0x2, %g1 240 LEON_PI(sta %g1, [%g0] ASI_LEON_MMUREGS) 241 SUN_PI_(sta %g1, [%g0] ASI_M_MMUREGS) 249 andn %g1, 0x2, %g1 250 LEON_PI(sta %g1, [%g0] ASI_LEON_MMUREGS) 251 SUN_PI_(sta %g1, [%g0] ASI_M_MMUREGS) 257 mov AC_M_SFSR, %g1 258 LEON_PI(lda [%g1] ASI_LEON_MMUREGS, %g1) 259 SUN_PI_(lda [%g1] ASI_M_MMUREGS, %g1) 260 andcc %g1, 0x2, %g0
H A D	helpers.S	`5 rdpr %otherwin, %g1 6 brz,pn %g1, 2f 9 rdpr %otherwin, %g1 10 brnz,pt %g1, 1b 30 rdpr %cwp, %g1 32 sub %g1, 1, %g3 42 2: wrpr %g1, %cwp`
H A D	una_asm_64.S	`19 srlx %g3, 56, %g1 21 4: stba %g1, [%o0] %asi 22 srlx %g3, 40, %g1 25 6: stba %g1, [%o0 + 2] %asi 27 srlx %g3, 16, %g1 30 9: stba %g1, [%o0 + 5] %asi 88 8: lduba [%o2 + 3] %asi, %g1 91 or %g7, %g1, %g7 102 12: lduba [%o2 + 3] %asi, %g1 104 sllx %g1, 32, %g1 106 or %g7, %g1, %g7 109 14: lduba [%o2 + 5] %asi, %g1 112 sllx %g1, 16, %g1 116 or %g7, %g1, %g7`
H A D	fpu_traps.S	22 1: TRAP_LOAD_THREAD_REG(%g6, %g1) 66 add %g6, TI_FPREGS + 0x80, %g1 90 ldda [%g1] ASI_BLK_S, %f32 117 add %g6, TI_FPREGS, %g1 132 ldda [%g1] ASI_BLK_S, %f0 150 add %g6, TI_FPREGS, %g1 170 ldda [%g1] ASI_BLK_S, %f0 171 ldda [%g1 + %g2] ASI_BLK_S, %f16 172 add %g1, 0x80, %g1 173 ldda [%g1] ASI_BLK_S, %f32 174 ldda [%g1 + %g2] ASI_BLK_S, %f48 207 TRAP_LOAD_THREAD_REG(%g6, %g1) 220 srlx %g3, 14, %g1 221 and %g1, 7, %g1 222 cmp %g1, 2 ! Unfinished FP-OP 224 sethi %hi(1 << 23), %g1 ! Inexact 225 andcc %g3, %g1, %g0 227 rdpr %tpc, %g1 228 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail 231 sethi %hi(FITOS_MASK), %g1 232 or %g1, %lo(FITOS_MASK), %g1 233 and %g3, %g1, %g1 236 cmp %g1, %g2 240 sethi %hi(fitos_table_1), %g1 242 or %g1, %lo(fitos_table_1), %g1 244 jmpl %g1 + %g2, %g0 282 sethi %hi(fitos_table_2), %g1 284 or %g1, %lo(fitos_table_2), %g1 287 jmpl %g1 + %g2, %g0 333 TRAP_LOAD_THREAD_REG(%g6, %g1) 337 rd %fprs, %g1 338 or %g3, %g1, %g3 361 andcc %g1, FPRS_DL, %g0 366 andcc %g1, FPRS_DU, %g0 371 5: mov SECONDARY_CONTEXT, %g1 374 661: stxa %g5, [%g1] ASI_DMMU 377 stxa %g5, [%g1] ASI_MMU
H A D	tsb.S	20 * %g1: TSB entry pointer 41 * %g1 -- PAGE_SIZE TSB entry address 101 * %g1 -- TSB entry address 152 ldx [%g7 + TRAP_PER_CPU_TSB_HUGE_TEMP], %g1 153 cmp %g1, -1 180 * %g1 -- TSB entry address 186 TSB_LOCK_TAG(%g1, %g2, %g7) 187 TSB_WRITE(%g1, %g5, %g6) 346 1: TSB_LOAD_TAG(%o0, %g1) 347 srlx %g1, 32, %o3 351 cmp %g1, %o1 355 TSB_CAS_TAG(%o0, %g1, %o3) 356 cmp %g1, %o3 379 rdpr %pstate, %g1 380 wrpr %g1, PSTATE_IE, %pstate 451 wrpr %g1, %pstate 468 add %o0, %o1, %g1 /* end of old tsb */ 506 cmp %o0, %g1 520 mov 1, %g1 522 sllx %g1, TSB_TAG_INVALID_BIT, %g1 525 stx %g1, [%o0 + 0x00] 526 stx %g1, [%o0 + 0x10] 527 stx %g1, [%o0 + 0x20] 528 stx %g1, [%o0 + 0x30] 530 stx %g1, [%o0 + 0x40] 531 stx %g1, [%o0 + 0x50] 532 stx %g1, [%o0 + 0x60] 533 stx %g1, [%o0 + 0x70] 535 stx %g1, [%o0 + 0x80] 536 stx %g1, [%o0 + 0x90] 537 stx %g1, [%o0 + 0xa0] 538 stx %g1, [%o0 + 0xb0] 540 stx %g1, [%o0 + 0xc0] 541 stx %g1, [%o0 + 0xd0] 542 stx %g1, [%o0 + 0xe0] 543 stx %g1, [%o0 + 0xf0] 557 mov 1, %g1 559 sllx %g1, TSB_TAG_INVALID_BIT, %g1 560 1: stxa %g1, [%o0 + 0x00] %asi 561 stxa %g1, [%o0 + 0x10] %asi 562 stxa %g1, [%o0 + 0x20] %asi 563 stxa %g1, [%o0 + 0x30] %asi 564 stxa %g1, [%o0 + 0x40] %asi 565 stxa %g1, [%o0 + 0x50] %asi 566 stxa %g1, [%o0 + 0x60] %asi 567 stxa %g1, [%o0 + 0x70] %asi 568 stxa %g1, [%o0 + 0x80] %asi 569 stxa %g1, [%o0 + 0x90] %asi 570 stxa %g1, [%o0 + 0xa0] %asi 571 stxa %g1, [%o0 + 0xb0] %asi 572 stxa %g1, [%o0 + 0xc0] %asi 573 stxa %g1, [%o0 + 0xd0] %asi 574 stxa %g1, [%o0 + 0xe0] %asi 575 stxa %g1, [%o0 + 0xf0] %asi
H A D	ivec.S	`5 * DATA 1: Address Argument 1, place in %g1 29 TRAP_LOAD_IRQ_WORK_PA(%g6, %g1) 37 mov 0x50, %g1 38 ldxa [%g1 + %g0] ASI_INTR_R, %g1`
H A D	etrap_64.S	33 etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1) 34 rdpr %tstate, %g1 35 or %g1, %g3, %g1 37 andcc %g1, TSTATE_PRIV, %g0 38 or %g1, %g3, %g1 46 and %g1, %g3, %g3 52 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE] 53 rdpr %tnpc, %g1 56 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC] 57 rdpr %tt, %g1 60 or %g3, %g1, %g1 61 st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC] 63 rdpr %cansave, %g1 64 brnz,pt %g1, etrap_save 67 rdpr %cwp, %g1 68 add %g1, 2, %g1 69 wrpr %g1, %cwp 125 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1] 175 TRAP_LOAD_THREAD_REG(%g6, %g1) 177 rdpr %tl, %g1 224 stx %g1, [%g2 + STACK_BIAS + 0x80] 234 rdpr %tstate, %g1 237 andcc %g1, TSTATE_PRIV, %g0
H A D	trampoline_64.S	42 BRANCH_IF_SUN4V(g1, niagara_startup) 43 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup) 44 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup) 55 mov DCR_BPE \| DCR_RPE \| DCR_SI \| DCR_IFPOE \| DCR_MS, %g1 56 wr %g1, %asr18 92 mov (LSU_CONTROL_IC \| LSU_CONTROL_DC \| LSU_CONTROL_IM \| LSU_CONTROL_DM), %g1 93 stxa %g1, [%g0] ASI_LSU_CONTROL 98 BRANCH_IF_SUN4V(g1, niagara_lock_tlb) 108 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 109 brnz,pn %g1, 1b 115 sethi %hi(tramp_stack), %g1 116 or %g1, %lo(tramp_stack), %g1 117 add %g1, TRAMP_STACK_SIZE, %g1 118 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp 136 BRANCH_IF_ANY_CHEETAH(g1,g5,2f) 158 sllx %l5, 22, %g1 160 add %l3, %g1, %g2 162 add %l4, %g1, %g2 191 sllx %l5, 22, %g1 193 add %l3, %g1, %g2 195 add %l4, %g1, %g2 283 sethi %hi(tramp_stack), %g1 284 or %g1, %lo(tramp_stack), %g1 285 add %g1, TRAMP_STACK_SIZE, %g1 286 sub %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp 315 mov PRIMARY_CONTEXT, %g1 317 661: stxa %g2, [%g1] ASI_DMMU 320 stxa %g2, [%g1] ASI_MMU 328 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1 329 brnz,pn %g1, 1b
H A D	head_64.S	94 rdpr %pstate, %g1 95 andn %g1, PSTATE_AM, %g1 96 wrpr %g1, 0x0, %pstate 318 sethi %hi(prom_root_compatible), %g1 319 or %g1, %lo(prom_root_compatible), %g1 324 ldub [%g1], %g4 330 add %g1, 1, %g1 332 sethi %hi(is_sun4v), %g1 333 or %g1, %lo(is_sun4v), %g1 335 stw %g7, [%g1] 381 sethi %hi(prom_cpu_compatible), %g1 382 or %g1, %lo(prom_cpu_compatible), %g1 387 ldub [%g1], %g4 393 add %g1, 1, %g1 397 89: sethi %hi(prom_cpu_compatible), %g1 398 or %g1, %lo(prom_cpu_compatible), %g1 403 ldub [%g1], %g4 409 add %g1, 1, %g1 411 sethi %hi(prom_cpu_compatible), %g1 412 or %g1, %lo(prom_cpu_compatible), %g1 413 ldub [%g1 + 6], %g2 420 70: ldub [%g1 + 7], %g2 439 91: sethi %hi(prom_cpu_compatible), %g1 440 or %g1, %lo(prom_cpu_compatible), %g1 441 ldub [%g1 + 17], %g2 451 sethi %hi(prom_cpu_compatible), %g1 452 or %g1, %lo(prom_cpu_compatible), %g1 457 ldub [%g1], %g4 463 add %g1, 1, %g1 474 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init) 475 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot) 476 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot) 486 mov DCR_BPE \| DCR_RPE \| DCR_SI \| DCR_IFPOE \| DCR_MS, %g1 487 wr %g1, %asr18 517 mov (LSU_CONTROL_IC\|LSU_CONTROL_DC\|LSU_CONTROL_IM\|LSU_CONTROL_DM), %g1 518 stxa %g1, [%g0] ASI_LSU_CONTROL 539 BRANCH_IF_SUN4V(g1, sun4v_init) 564 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup) 570 sethi %hi(tlb_type), %g1 571 stw %g2, [%g1 + %lo(tlb_type)] 574 sethi %hi(sun4v_chip_type), %g1 575 lduw [%g1 + %lo(sun4v_chip_type)], %g1 576 cmp %g1, SUN4V_CHIP_NIAGARA1 578 cmp %g1, SUN4V_CHIP_NIAGARA2 581 cmp %g1, SUN4V_CHIP_NIAGARA3 584 cmp %g1, SUN4V_CHIP_NIAGARA4 587 cmp %g1, SUN4V_CHIP_NIAGARA5 590 cmp %g1, SUN4V_CHIP_SPARC_M6 593 cmp %g1, SUN4V_CHIP_SPARC_M7 642 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) 646 1: sethi %hi(tlb_type), %g1 647 stw %g2, [%g1 + %lo(tlb_type)] 662 sethi %hi(tlb_type), %g1 663 stw %g2, [%g1 + %lo(tlb_type)] 671 mov 1, %g1 672 sllx %g1, THREAD_SHIFT, %g1 673 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 674 add %g6, %g1, %sp 799 mov PRIMARY_CONTEXT, %g1 801 661: stxa %g2, [%g1] ASI_DMMU 804 stxa %g2, [%g1] ASI_MMU
H A D	syscalls.S	5 set sys_execve, %g1 6 jmpl %g1, %g0 10 set sys_execveat, %g1 11 jmpl %g1, %g0 18 set compat_sys_execve, %g1 19 jmpl %g1, %g0 23 set compat_sys_execveat, %g1 24 jmpl %g1, %g0 141 rdpr %otherwin, %g1 143 add %g3, %g1, %g3 163 ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 173 cmp %g1, NR_syscalls 177 sll %g1, 2, %l4 193 ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 203 cmp %g1, NR_syscalls 207 sll %g1, 2, %l4 222 cmp %g1, NR_syscalls ! IEU1 Group 225 sll %g1, 2, %l4 ! IEU0 Group 246 cmp %g1, NR_syscalls ! IEU1 Group 249 sll %g1, 2, %l4 ! IEU0 Group
H A D	ktlb.S	34 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load) 49 TSB_LOCK_TAG(%g1, %g2, %g7) 50 TSB_WRITE(%g1, %g5, %g6) 96 TSB_LOCK_TAG(%g1, %g2, %g7) 98 TSB_WRITE(%g1, %g5, %g6) 106 TSB_LOCK_TAG(%g1, %g2, %g7) 108 TSB_WRITE(%g1, %g5, %g6) 121 TSB_LOCK_TAG(%g1, %g2, %g7) 122 TSB_WRITE(%g1, %g5, %g6) 142 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load) 145 KERN_TSB4M_LOOKUP_TL1(%g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load) 157 TSB_LOCK_TAG(%g1, %g2, %g7) 158 TSB_WRITE(%g1, %g5, %g6) 209 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
H A D	head_32.S	149 set lvl14_save, %g1 151 sub %g1, %l6, %g1 ! translate to physical 154 std %g4, [%g1] 156 std %g4, [%g1+8] 158 rd %tbr, %g1 159 andn %g1, 0xfff, %g1 ! proms trap table base 161 or %g1, %g2, %g2 216 lda [%g0] ASI_M_MMUREGS, %g1 217 andcc %g1, 1, %g0 309 set AC_M_CTPR, %g1 310 lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr 311 sll %g1, 0x4, %g1 ! make physical addr 312 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table 313 srl %g1, 0x4, %g1 314 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl 316 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 317 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 325 lda [%g0] ASI_LEON_MMUREGS, %g1 326 andcc %g1, 1, %g0 333 set AC_M_CTPR, %g1 334 lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr 335 sll %g1, 0x4, %g1 ! make physical addr 336 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table 337 srl %g1, 0x4, %g1 338 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl 340 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 341 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 348 set execute_in_high_mem, %g1 349 jmpl %g1, %g0 363 sethi %hi(prom_vector_p), %g1 364 st %o0, [%g1 + %lo(prom_vector_p)] 366 sethi %hi(linux_dbvec), %g1 367 st %o1, [%g1 + %lo(linux_dbvec)] 429 ldub [%g2 + %lo(boot_cpu_id)], %g1 430 cmp %g1, 0xff ! unset means first CPU 435 rd %asr17, %g1 436 srl %g1, 28, %g1 439 stub %g1, [%g2 + %lo(boot_cpu_id)] 514 set init_thread_union, %g1 516 add %g1, %g2, %sp 572 mov 2, %g1 573 wr %g1, 0x0, %wim ! make window 1 invalid
H A D	hvtramp.S	`43 sethi %hi(sparc64_ttable_tl0), %g1 44 wrpr %g1, %tba 48 lduw [%l0 + HVTRAMP_DESCR_CPU], %g1 50 stxa %g1, [%g2] ASI_SCRATCHPAD`
H A D	rtrap_64.S	`155 rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 234 rdpr %cwp, %g1 236 sub %g1, 1, %g1 238 wrpr %g1, %cwp 254 add %g1, 1, %g1 255 wrpr %g1, 0x0, %cwp 259 rdpr %canrestore, %g1 260 wrpr %g1, 0x0, %cleanwin 264 kern_rtt: rdpr %canrestore, %g1 265 brz,pn %g1, kern_rtt_fill 301 rd %fprs, %g1 303 wr %g1, FPRS_FEF, %fprs 304 ldx [%o1 + %o5], %g1 317 wr %g1, 0, %gsr`
H A D	sun4v_ivec.S	37 * 2nd 64-bit word: 64-bit arg, load into %g1 43 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1 99 TRAP_LOAD_IRQ_WORK_PA(%g1, %g4) 111 1: ldx [%g1], %g2 113 stx %g4, [%g1] 142 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1 143 brnz,pn %g1, sun4v_res_mondo_queue_full 148 /* Remember this entry's offset in %g1. / 149 mov %g2, %g1 190 mov %g1, %g4 253 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1 254 brnz,pn %g1, sun4v_nonres_mondo_queue_full 259 / Remember this entry's offset in %g1. */ 260 mov %g2, %g1 301 mov %g1, %g4
H A D	etrap_32.S	`39 tsetup_7win_patch4: and %g1, 0x7f, %g1 104 ld [%curptr + TI_UWINMASK], %g1 105 orcc %g0, %g1, %g0 163 orn %g0, %t_twinmask, %g1 ! negate trap win mask into %g1 198 * is in %g1 upon entry to here. 202 and %g1, 0xff, %g1 ! patched on 7win Sparcs, mask 209 andn %g1, %g2, %g1 ! clear this bit in %g1 210 st %g1, [%curptr + TI_UWINMASK] 227 #define glob_tmp g1`
H A D	spiterrs.S	`16 mov UDBE_UE, %g1 20 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the ESTATE 55 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE 66 andcc %g3, %g1, %g3 ! UDBE_UE or UDBE_CE 142 * %g1, and we only disable CE error reporting unlike UE 150 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */ 152 mov UDBE_CE, %g1`
H A D	traps_64.c	980 "or %0, %2, %%g1\n\t" cheetah_flush_icache() 981 "stxa %%g1, [%%g0] %1\n\t" cheetah_flush_icache() 985 : "g1"); cheetah_flush_icache() 1318 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_fecc_handler() 1319 "or %%g1, %1, %%g1\n\t" cheetah_fecc_handler() 1320 "stxa %%g1, [%%g0] %0\n\t" cheetah_fecc_handler() 1325 : "g1"); cheetah_fecc_handler() 1328 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_fecc_handler() 1329 "or %%g1, %1, %%g1\n\t" cheetah_fecc_handler() 1330 "stxa %%g1, [%%g0] %0\n\t" cheetah_fecc_handler() 1335 : "g1"); cheetah_fecc_handler() 1380 "andn %0, %1, %%g1\n\t" cheetah_fix_ce() 1381 "stxa %%g1, [%%g0] %2\n\t" cheetah_fix_ce() 1386 : "g1"); cheetah_fix_ce() 1501 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_cee_handler() 1502 "or %%g1, %1, %%g1\n\t" cheetah_cee_handler() 1503 "stxa %%g1, [%%g0] %0\n\t" cheetah_cee_handler() 1508 : "g1"); cheetah_cee_handler() 1517 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_cee_handler() 1518 "or %%g1, %1, %%g1\n\t" cheetah_cee_handler() 1519 "stxa %%g1, [%%g0] %0\n\t" cheetah_cee_handler() 1524 : "g1"); cheetah_cee_handler() 1555 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_deferred_handler() 1556 "or %%g1, %1, %%g1\n\t" cheetah_deferred_handler() 1557 "stxa %%g1, [%%g0] %0\n\t" cheetah_deferred_handler() 1562 : "g1"); cheetah_deferred_handler() 1565 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_deferred_handler() 1566 "or %%g1, %1, %%g1\n\t" cheetah_deferred_handler() 1567 "stxa %%g1, [%%g0] %0\n\t" cheetah_deferred_handler() 1572 : "g1"); cheetah_deferred_handler() 1629 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_deferred_handler() 1630 "or %%g1, %1, %%g1\n\t" cheetah_deferred_handler() 1631 "stxa %%g1, [%%g0] %0\n\t" cheetah_deferred_handler() 1636 : "g1"); cheetah_deferred_handler() 1645 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_deferred_handler() 1646 "or %%g1, %1, %%g1\n\t" cheetah_deferred_handler() 1647 "stxa %%g1, [%%g0] %0\n\t" cheetah_deferred_handler() 1652 : "g1"); cheetah_deferred_handler() 1747 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" cheetah_plus_parity_error() 1748 "or %%g1, %1, %%g1\n\t" cheetah_plus_parity_error() 1749 "stxa %%g1, [%%g0] %0\n\t" cheetah_plus_parity_error() 1754 : "g1"); cheetah_plus_parity_error()
H A D	entry.S	`701 * the %psr in register %g1. 707 srl %l0, 20, %g1 ! give user 708 and %g1, 0xf, %g1 ! only ICC bits in %psr 712 /* The setcc software trap. The user has condition codes in %g1 720 sll %g1, 0x14, %l4 953 ld [%sp + STACKFRAME_SZ + PT_G1], %g1 962 cmp %g1, NR_syscalls 966 sll %g1, 2, %l4 1006 cmp %g1, NR_syscalls 1008 sll %g1, 2, %l4 1086 ld [%o1], %g1 1088 andcc %g1, %g4, %g0 1250 mov 1, %g1 ! signal EFAULT condition 1365 661: rd %tbr, %g1 1366 srl %g1, 12, %o0`
H A D	sun4m_irq.c	`316 __asm__ __volatile__("mov 0x500, %%g1\n\t" sun4m_nmi() 317 "lda [%%g1] 0x4, %0\n\t" sun4m_nmi() 318 "mov 0x600, %%g1\n\t" sun4m_nmi() 319 "lda [%%g1] 0x4, %1\n\t" : sun4m_nmi()`
H A D	irq_64.c	`959 " ldxa [%%g0] %0, %%g1\n" kill_prom_timer() 960 " ldxa [%%g2] %1, %%g1\n" kill_prom_timer() 965 : "g1", "g2"); kill_prom_timer() 1139 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" init_IRQ() 1140 "or %%g1, %0, %%g1\n\t" init_IRQ() 1141 "wrpr %%g1, 0x0, %%pstate" init_IRQ() 1144 : "g1"); init_IRQ()`
H A D	signal_32.c	`307 /* mov __NR_sigreturn, %g1 / setup_frame() 404 / mov __NR_sigreturn, %g1 */ setup_rt_frame()`
H A D	signal32.c	`540 err = __put_user(0x821020d8, &sf->insns[0]); /mov __NR_sigreturn, %g1/ setup_frame32() 671 /* mov __NR_rt_sigreturn, %g1 */ setup_rt_frame32()`
H A D	smp_64.c	`421 "mov 0x20, %%g1\n\t" spitfire_xcall_helper() 422 "ldxa [%%g1] 0x7f, %%g0\n\t" spitfire_xcall_helper() 428 : "g1"); spitfire_xcall_helper()`
H A D	time_64.c	`205 : "g1", "g2"); stick_init_tick()`
H A D	wof.S	`245 STORE_PT_ALL(sp, t_psr, t_pc, t_npc, g1)`
H A D	kprobes.c	`461 register unsigned long orig_fp asm("g1"); jprobe_return()`
H A D	process_64.c	`174 printk("g0: %016lx g1: %016lx g2: %016lx g3: %016lx\n", show_regs()`
/linux-4.4.14/arch/sparc/include/asm/
H A D	ttable.h	273 sub %g1, 2, %g1; \ 275 wrpr %g1, %cwp; \ 281 add %sp, STACK_BIAS + 0x00, %g1; \ 282 stxa %l0, [%g1 + %g0] ASI; \ 284 stxa %l1, [%g1 + %g3] ASI; \ 285 add %g1, 0x10, %g1; \ 286 stxa %l2, [%g1 + %g0] ASI; \ 287 stxa %l3, [%g1 + %g3] ASI; \ 288 add %g1, 0x10, %g1; \ 289 stxa %l4, [%g1 + %g0] ASI; \ 290 stxa %l5, [%g1 + %g3] ASI; \ 291 add %g1, 0x10, %g1; \ 292 stxa %l6, [%g1 + %g0] ASI; \ 293 stxa %l7, [%g1 + %g3] ASI; \ 294 add %g1, 0x10, %g1; \ 295 stxa %i0, [%g1 + %g0] ASI; \ 296 stxa %i1, [%g1 + %g3] ASI; \ 297 add %g1, 0x10, %g1; \ 298 stxa %i2, [%g1 + %g0] ASI; \ 299 stxa %i3, [%g1 + %g3] ASI; \ 300 add %g1, 0x10, %g1; \ 301 stxa %i4, [%g1 + %g0] ASI; \ 302 stxa %i5, [%g1 + %g3] ASI; \ 303 add %g1, 0x10, %g1; \ 304 stxa %i6, [%g1 + %g0] ASI; \ 305 stxa %i7, [%g1 + %g3] ASI; \ 331 sub %g1, 2, %g1; \ 333 wrpr %g1, %cwp; \ 342 ldub [%g6 + TI_WSAVED], %g1; \ 343 sll %g1, 3, %g3; \ 346 sll %g1, 7, %g3; \ 364 add %g1, 1, %g1; \ 365 stb %g1, [%g6 + TI_WSAVED]; \ 367 rdpr %cwp, %g1; \ 368 sub %g1, 2, %g1; \ 370 wrpr %g1, %cwp; \ 381 add %sp, 0x08, %g1; \ 382 stwa %l2, [%g1 + %g0] ASI; \ 383 stwa %l3, [%g1 + %g3] ASI; \ 384 add %g1, 0x08, %g1; \ 385 stwa %l4, [%g1 + %g0] ASI; \ 386 stwa %l5, [%g1 + %g3] ASI; \ 387 add %g1, 0x08, %g1; \ 388 stwa %l6, [%g1 + %g0] ASI; \ 389 stwa %l7, [%g1 + %g3] ASI; \ 390 add %g1, 0x08, %g1; \ 391 stwa %i0, [%g1 + %g0] ASI; \ 392 stwa %i1, [%g1 + %g3] ASI; \ 393 add %g1, 0x08, %g1; \ 394 stwa %i2, [%g1 + %g0] ASI; \ 395 stwa %i3, [%g1 + %g3] ASI; \ 396 add %g1, 0x08, %g1; \ 397 stwa %i4, [%g1 + %g0] ASI; \ 398 stwa %i5, [%g1 + %g3] ASI; \ 399 add %g1, 0x08, %g1; \ 400 stwa %i6, [%g1 + %g0] ASI; \ 401 stwa %i7, [%g1 + %g3] ASI; \ 430 sub %g1, 2, %g1; \ 432 wrpr %g1, %cwp; \ 441 ldub [%g6 + TI_WSAVED], %g1; \ 442 sll %g1, 3, %g3; \ 445 sll %g1, 7, %g3; \ 463 add %g1, 1, %g1; \ 464 stb %g1, [%g6 + TI_WSAVED]; \ 466 rdpr %cwp, %g1; \ 467 sub %g1, 2, %g1; \ 469 wrpr %g1, %cwp; \ 512 rdpr %cwp, %g1; \ 513 sub %g1, 1, %g1; \ 514 wrpr %g1, %cwp; \ 532 add %g1, 1, %g1; \ 534 wrpr %g1, %cwp; \ 541 add %sp, STACK_BIAS + 0x00, %g1; \ 542 ldxa [%g1 + %g0] ASI, %l0; \ 545 ldxa [%g1 + %g2] ASI, %l1; \ 547 ldxa [%g1 + %g3] ASI, %l2; \ 548 ldxa [%g1 + %g5] ASI, %l3; \ 549 add %g1, 0x20, %g1; \ 550 ldxa [%g1 + %g0] ASI, %l4; \ 551 ldxa [%g1 + %g2] ASI, %l5; \ 552 ldxa [%g1 + %g3] ASI, %l6; \ 553 ldxa [%g1 + %g5] ASI, %l7; \ 554 add %g1, 0x20, %g1; \ 555 ldxa [%g1 + %g0] ASI, %i0; \ 556 ldxa [%g1 + %g2] ASI, %i1; \ 557 ldxa [%g1 + %g3] ASI, %i2; \ 558 ldxa [%g1 + %g5] ASI, %i3; \ 559 add %g1, 0x20, %g1; \ 560 ldxa [%g1 + %g0] ASI, %i4; \ 561 ldxa [%g1 + %g2] ASI, %i5; \ 562 ldxa [%g1 + %g3] ASI, %i6; \ 563 ldxa [%g1 + %g5] ASI, %i7; \ 609 add %sp, 0x10, %g1; \ 610 lduwa [%g1 + %g0] ASI, %l4; \ 611 lduwa [%g1 + %g2] ASI, %l5; \ 612 lduwa [%g1 + %g3] ASI, %l6; \ 613 lduwa [%g1 + %g5] ASI, %l7; \ 614 add %g1, 0x10, %g1; \ 615 lduwa [%g1 + %g0] ASI, %i0; \ 616 lduwa [%g1 + %g2] ASI, %i1; \ 617 lduwa [%g1 + %g3] ASI, %i2; \ 618 lduwa [%g1 + %g5] ASI, %i3; \ 619 add %g1, 0x10, %g1; \ 620 lduwa [%g1 + %g0] ASI, %i4; \ 621 lduwa [%g1 + %g2] ASI, %i5; \ 622 lduwa [%g1 + %g3] ASI, %i6; \ 623 lduwa [%g1 + %g5] ASI, %i7; \
H A D	visasm.h	`12 /* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc / 19 sethi %hi(VISenter), %g1; \ 20 jmpl %g1 + %lo(VISenter), %g0; \ 27 / Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc. 54 " sethi %%hi(VISenter), %%g1\n" save_and_clear_fpu() 55 " jmpl %%g1 + %%lo(VISenter), %%g0\n" save_and_clear_fpu() 60 "o5", "g1", "g2", "g3", "g7", "cc"); save_and_clear_fpu()`
H A D	switch_to_64.h	`39 "ldub [%4 + %8], %%g1\n\t" \ 40 "wrpr %%g1, %%cwp\n\t" \ 51 "sethi %%hi(ret_from_fork), %%g1\n\t" \ 52 "jmpl %%g1 + %%lo(ret_from_fork), %%g0\n\t" \ 62 "g1", "g2", "g3", "g7", \`
H A D	ross.h	`84 * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1 88 * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr 103 __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 / get_ross_icr() 104 "mov %%g1, %0\n\t" get_ross_icr() 107 : "g1", "memory"); get_ross_icr() 114 __asm__ __volatile__("or %%g0, %0, %%g1\n\t" put_ross_icr() 115 ".word 0xbf806000\n\t" / wr %g1, 0x0, %iccr */ put_ross_icr() 121 : "g1", "memory"); put_ross_icr()`
H A D	spinlock_32.h	`82 register arch_rwlock_t lp asm("g1"); __arch_read_lock() 87 " ldstub [%%g1 + 3], %%g2\n" __arch_read_lock() 102 register arch_rwlock_t lp asm("g1"); __arch_read_unlock() 107 " ldstub [%%g1 + 3], %%g2\n" __arch_read_unlock() 122 register arch_rwlock_t lp asm("g1"); arch_write_lock() 127 " ldstub [%%g1 + 3], %%g2\n" arch_write_lock() 165 register arch_rwlock_t lp asm("g1"); __arch_read_trylock() 171 " ldstub [%%g1 + 3], %%g2\n" __arch_read_trylock()`
H A D	sfp-machine_32.h	`112 register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \ 117 "addx %r2,%3,%%g1\n\t" \ 128 : "cc", "g1", "g2"); \ 137 register USItype _t1 __asm__ ("g1"), _t2 __asm__ ("g2"); \ 142 "subx %r2,%3,%%g1\n\t" \ 153 : "cc", "g1", "g2"); \`
H A D	winmacro.h	`44 ld [%base_reg + STACKFRAME_SZ + PT_G1], %g1; \ 71 st %g1, [%base_reg + STACKFRAME_SZ + PT_G1]; \`
H A D	checksum_32.h	`48 register int l asm("g1") = len; csum_partial_copy_nocheck() 67 register int l asm("g1") = len; csum_partial_copy_from_user() 95 register int l asm("g1") = len; csum_partial_copy_to_user()`
H A D	processor_32.h	`83 register unsigned long zero asm("g1"); start_thread()`
H A D	switch_to_32.h	`96 : "g1", "g2", "g3", "g4", "g5", "g7", \`
H A D	syscall.h	`17 /* The system call number is given by the user in %g1 */ syscall_get_nr()`
H A D	tsb.h	`13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1 17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4`
H A D	uaccess_32.h	`359 "g1", "g2", "g3", "g4", "g5", "g7", "cc"); __clear_user()`
/linux-4.4.14/arch/sparc/mm/
H A D	hypersparc.S	29 sethi %hi(vac_line_size), %g1 30 ld [%g1 + %lo(vac_line_size)], %g2 41 ld [%o0 + AOFF_mm_context], %g1 42 cmp %g1, -1 47 sethi %hi(vac_line_size), %g1 48 ld [%g1 + %lo(vac_line_size)], %o1 51 add %o1, %o1, %g1 52 add %o1, %g1, %g2 64 sta %g0, [%o0 + %g1] ASI_M_FLUSH_USER 79 ld [%o0 + AOFF_mm_context], %g1 80 cmp %g1, -1 85 sethi %hi(vac_line_size), %g1 86 ld [%g1 + %lo(vac_line_size)], %o4 95 add %o4, %o5, %g1 97 add %o4, %g1, %g2 114 sta %g0, [%o3 + %g1] ASI_M_FLUSH_USER 142 sta %g0, [%o2 + %g1] ASI_M_FLUSH_PAGE 174 sethi %hi(vac_line_size), %g1 175 ld [%g1 + %lo(vac_line_size)], %o4 181 lda [%o5] ASI_M_FLUSH_PROBE, %g1 182 orcc %g0, %g1, %g0 186 add %o4, %o5, %g1 187 add %o4, %g1, %g2 199 sta %g0, [%o1 + %g1] ASI_M_FLUSH_PAGE 222 sethi %hi(vac_line_size), %g1 223 ld [%g1 + %lo(vac_line_size)], %o4 228 add %o4, %o5, %g1 231 add %o4, %g1, %g2 244 sta %g0, [%o0 + %g1] ASI_M_FLUSH_PAGE 252 mov SRMMU_FAULT_STATUS, %g1 254 lda [%g1] ASI_M_MMUREGS, %g0 266 mov 0x400, %g1 267 sta %g0, [%g1] ASI_M_FLUSH_PROBE 272 mov SRMMU_CTX_REG, %g1 274 lda [%g1] ASI_M_MMUREGS, %g5 280 sta %o1, [%g1] ASI_M_MMUREGS 284 sta %g5, [%g1] ASI_M_MMUREGS 288 mov SRMMU_CTX_REG, %g1 290 lda [%g1] ASI_M_MMUREGS, %g5 296 sta %o3, [%g1] ASI_M_MMUREGS 307 sta %g5, [%g1] ASI_M_MMUREGS 311 mov SRMMU_CTX_REG, %g1 318 lda [%g1] ASI_M_MMUREGS, %g5 319 sta %o3, [%g1] ASI_M_MMUREGS 323 sta %g5, [%g1] ASI_M_MMUREGS 330 clr %g1 358 mov 16, %g1 375 subcc %g1, 1, %g1
H A D	ultra.S	136 rdpr %pstate, %g1 137 wrpr %g1, PSTATE_IE, %pstate 146 wrpr %g1, 0, %pstate 156 sethi %hi(PAGE_OFFSET), %g1 159 ldx [%g1 + %lo(PAGE_OFFSET)], %g1 160 add %o0, %g1, %o0 181 sethi %hi(PAGE_OFFSET), %g1 182 ldx [%g1 + %lo(PAGE_OFFSET)], %g1 183 sub %o0, %g1, %o0 ! physical address 290 sethi %hi(PAGE_OFFSET), %g1 291 ldx [%g1 + %lo(PAGE_OFFSET)], %g1 292 sub %o0, %g1, %o0 340 sllx %o1, 3, %g1 343 1: sub %g1, (1 << 3), %g1 344 ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit / 352 brnz,pt %g1, 1b 362 mov %o0, %g1 363 sub %o1, %g1, %g2 365 1: add %g1, %g2, %o0 / ARG0: virtual address / 387 1: lduw [%o1], %g1 388 stw %g1, [%o0] 440 %g1 address arg 1 (tlb page and range flushes) 475 /* %g5=context, %g1=vaddr / 483 andcc %g1, 0x1, %g0 485 andn %g1, 0x1, %g5 498 andn %g1, %g2, %g1 500 sub %g7, %g1, %g3 503 or %g1, 0x20, %g1 ! Nucleus 504 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP 505 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP 552 sethi %hi(global_cpu_snapshot), %g1 553 or %g1, %lo(global_cpu_snapshot), %g1 556 add %g1, %g3, %g1 558 stx %g7, [%g1 + GR_SNAP_TSTATE] 560 stx %g7, [%g1 + GR_SNAP_TPC] 562 stx %g7, [%g1 + GR_SNAP_TNPC] 563 stx %o7, [%g1 + GR_SNAP_O7] 564 stx %i7, [%g1 + GR_SNAP_I7] 571 stx %g7, [%g1 + GR_SNAP_RPC] 577 stx %g3, [%g1 + GR_SNAP_THREAD] 582 sethi %hi(global_cpu_snapshot), %g1 583 or %g1, %lo(global_cpu_snapshot), %g1 586 add %g1, %g3, %g1 588 stx %g7, [%g1 + (4 8)] 590 stx %g7, [%g1 + (0 * 8)] 595 sethi %hi(global_cpu_snapshot), %g1 596 or %g1, %lo(global_cpu_snapshot), %g1 599 add %g1, %g3, %g1 602 stx %g7, [%g1 + (4 * 8)] 605 stx %g7, [%g1 + (5 * 8)] 608 stx %g7, [%g1 + (6 * 8)] 611 stx %g7, [%g1 + (7 * 8)] 620 stx %o1, [%g1 + (3 * 8)] 624 stx %o1, [%g1 + (2 * 8)] 628 stx %o1, [%g1 + (1 * 8)] 632 stx %o1, [%g1 + (0 * 8)] 643 xcall_flush_dcache_page_cheetah: /* %g1 == physical page address / 646 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE 655 xcall_flush_dcache_page_spitfire: / %g1 == physical page address 659 srlx %g1, (13 - 2), %g1 ! Form tag comparitor 666 cmp %g2, %g1 704 /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable / 708 mov %o3, %g1 722 mov %g1, %o3 729 / %g5=ctx, %g1=vaddr / 733 mov %g1, %o0 / ARG0: virtual address / 750 / %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch / 753 andn %g1, %g2, %g1 755 sub %g7, %g1, %g3 761 1: add %g1, %g3, %o0 / ARG0: virtual address */
H A D	viking.S	39 srl %g3, 12, %g1 ! ppage >> 12 56 cmp %g3, %g1 ! ptag == ppage? 115 ld [%o0 + AOFF_mm_context], %g1 116 cmp %g1, -1 128 mov 0x400, %g1 130 sta %g0, [%g1] ASI_M_FLUSH_PROBE 133 mov SRMMU_CTX_REG, %g1 135 lda [%g1] ASI_M_MMUREGS, %g5 141 sta %o1, [%g1] ASI_M_MMUREGS 144 sta %g5, [%g1] ASI_M_MMUREGS 152 mov SRMMU_CTX_REG, %g1 154 lda [%g1] ASI_M_MMUREGS, %g5 160 sta %o3, [%g1] ASI_M_MMUREGS 169 sta %g5, [%g1] ASI_M_MMUREGS 177 mov SRMMU_CTX_REG, %g1 179 lda [%g1] ASI_M_MMUREGS, %g5 185 sta %o3, [%g1] ASI_M_MMUREGS 188 sta %g5, [%g1] ASI_M_MMUREGS 208 mov 0x400, %g1 209 sta %g0, [%g1] ASI_M_FLUSH_PROBE 222 mov SRMMU_CTX_REG, %g1 224 lda [%g1] ASI_M_MMUREGS, %g5 226 sta %o1, [%g1] ASI_M_MMUREGS 228 sta %g5, [%g1] ASI_M_MMUREGS 241 mov SRMMU_CTX_REG, %g1 244 lda [%g1] ASI_M_MMUREGS, %g5 246 sta %o3, [%g1] ASI_M_MMUREGS 254 sta %g5, [%g1] ASI_M_MMUREGS 267 mov SRMMU_CTX_REG, %g1 270 lda [%g1] ASI_M_MMUREGS, %g5 272 sta %o3, [%g1] ASI_M_MMUREGS 274 sta %g5, [%g1] ASI_M_MMUREGS
H A D	tsunami.S	`69 mov SRMMU_CTX_REG, %g1 74 lda [%g1] ASI_M_MMUREGS, %g5 75 sta %o3, [%g1] ASI_M_MMUREGS 84 sta %g5, [%g1] ASI_M_MMUREGS 98 or %g0, (PAGE_SIZE >> 8), %g1 108 subcc %g1, 1, %g1`
H A D	swift.S	`59 rd %psr, %g1 60 andn %g1, PSR_ET, %g3 99 wr %g1, 0x0, %psr 125 rd %psr, %g1 126 andn %g1, PSR_ET, %g3 165 wr %g1, 0x0, %psr 237 mov SRMMU_CTX_REG, %g1 247 lda [%g1] ASI_M_MMUREGS, %g5 248 sta %o3, [%g1] ASI_M_MMUREGS 251 sta %g5, [%g1] ASI_M_MMUREGS`
H A D	leon_mm.c	`223 "mov 0x08, %%g1\n\t" leon3_getCacheRegs() 224 "lda [%%g1] %3, %1\n\t" leon3_getCacheRegs() 225 "mov 0x0c, %%g1\n\t" leon3_getCacheRegs() 226 "lda [%%g1] %3, %2\n\t" leon3_getCacheRegs() 230 : "g1" /* clobber list */ leon3_getCacheRegs()`
H A D	init_64.c	234 "and %%g7, %1, %%g1\n\t" set_dcache_dirty() 235 "or %%g1, %0, %%g1\n\t" set_dcache_dirty() 236 "casx [%2], %%g7, %%g1\n\t" set_dcache_dirty() 237 "cmp %%g7, %%g1\n\t" set_dcache_dirty() 242 : "g1", "g7"); set_dcache_dirty() 252 "srlx %%g7, %4, %%g1\n\t" clear_dcache_dirty_cpu() 253 "and %%g1, %3, %%g1\n\t" clear_dcache_dirty_cpu() 254 "cmp %%g1, %0\n\t" clear_dcache_dirty_cpu() 256 " andn %%g7, %1, %%g1\n\t" clear_dcache_dirty_cpu() 257 "casx [%2], %%g7, %%g1\n\t" clear_dcache_dirty_cpu() 258 "cmp %%g7, %%g1\n\t" clear_dcache_dirty_cpu() 266 : "g1", "g7"); clear_dcache_dirty_cpu()
/linux-4.4.14/lib/mpi/
H A D	longlong.h	1029 "divscc %3,%4,%%g1\n" \ 1030 "divscc %%g1,%4,%%g1\n" \ 1031 "divscc %%g1,%4,%%g1\n" \ 1032 "divscc %%g1,%4,%%g1\n" \ 1033 "divscc %%g1,%4,%%g1\n" \ 1034 "divscc %%g1,%4,%%g1\n" \ 1035 "divscc %%g1,%4,%%g1\n" \ 1036 "divscc %%g1,%4,%%g1\n" \ 1037 "divscc %%g1,%4,%%g1\n" \ 1038 "divscc %%g1,%4,%%g1\n" \ 1039 "divscc %%g1,%4,%%g1\n" \ 1040 "divscc %%g1,%4,%%g1\n" \ 1041 "divscc %%g1,%4,%%g1\n" \ 1042 "divscc %%g1,%4,%%g1\n" \ 1043 "divscc %%g1,%4,%%g1\n" \ 1044 "divscc %%g1,%4,%%g1\n" \ 1045 "divscc %%g1,%4,%%g1\n" \ 1046 "divscc %%g1,%4,%%g1\n" \ 1047 "divscc %%g1,%4,%%g1\n" \ 1048 "divscc %%g1,%4,%%g1\n" \ 1049 "divscc %%g1,%4,%%g1\n" \ 1050 "divscc %%g1,%4,%%g1\n" \ 1051 "divscc %%g1,%4,%%g1\n" \ 1052 "divscc %%g1,%4,%%g1\n" \ 1053 "divscc %%g1,%4,%%g1\n" \ 1054 "divscc %%g1,%4,%%g1\n" \ 1055 "divscc %%g1,%4,%%g1\n" \ 1056 "divscc %%g1,%4,%%g1\n" \ 1057 "divscc %%g1,%4,%%g1\n" \ 1058 "divscc %%g1,%4,%%g1\n" \ 1059 "divscc %%g1,%4,%%g1\n" \ 1060 "divscc %%g1,%4,%0\n" \ 1070 : "%g1" __AND_CLOBBER_CC) 1081 "andcc %%g0,0,%%g1 ! Don't move this insn\n" \ 1082 "mulscc %%g1,%3,%%g1\n" \ 1083 "mulscc %%g1,%3,%%g1\n" \ 1084 "mulscc %%g1,%3,%%g1\n" \ 1085 "mulscc %%g1,%3,%%g1\n" \ 1086 "mulscc %%g1,%3,%%g1\n" \ 1087 "mulscc %%g1,%3,%%g1\n" \ 1088 "mulscc %%g1,%3,%%g1\n" \ 1089 "mulscc %%g1,%3,%%g1\n" \ 1090 "mulscc %%g1,%3,%%g1\n" \ 1091 "mulscc %%g1,%3,%%g1\n" \ 1092 "mulscc %%g1,%3,%%g1\n" \ 1093 "mulscc %%g1,%3,%%g1\n" \ 1094 "mulscc %%g1,%3,%%g1\n" \ 1095 "mulscc %%g1,%3,%%g1\n" \ 1096 "mulscc %%g1,%3,%%g1\n" \ 1097 "mulscc %%g1,%3,%%g1\n" \ 1098 "mulscc %%g1,%3,%%g1\n" \ 1099 "mulscc %%g1,%3,%%g1\n" \ 1100 "mulscc %%g1,%3,%%g1\n" \ 1101 "mulscc %%g1,%3,%%g1\n" \ 1102 "mulscc %%g1,%3,%%g1\n" \ 1103 "mulscc %%g1,%3,%%g1\n" \ 1104 "mulscc %%g1,%3,%%g1\n" \ 1105 "mulscc %%g1,%3,%%g1\n" \ 1106 "mulscc %%g1,%3,%%g1\n" \ 1107 "mulscc %%g1,%3,%%g1\n" \ 1108 "mulscc %%g1,%3,%%g1\n" \ 1109 "mulscc %%g1,%3,%%g1\n" \ 1110 "mulscc %%g1,%3,%%g1\n" \ 1111 "mulscc %%g1,%3,%%g1\n" \ 1112 "mulscc %%g1,%3,%%g1\n" \ 1113 "mulscc %%g1,%3,%%g1\n" \ 1114 "mulscc %%g1,0,%%g1\n" \ 1115 "add %%g1,%%g2,%0\n" \ 1121 : "%g1", "%g2" __AND_CLOBBER_CC) 1127 "mov 32,%%g1\n\t" \ 1133 "subcc %%g1,1,%%g1\n\t" \ 1143 "subcc %%g1,1,%%g1\n\t" \ 1154 "0" ((USItype)(n0)) : "%g1", "cc")
/linux-4.4.14/arch/sparc/crypto/
H A D	aes_asm.S	914 ldx [%o0 + 0x00], %g1 922 xor %g1, %g3, %g3 926 xor %g1, %o4, %g3 943 xor %g1, %g3, %g3 957 ldx [%o0 + 0x00], %g1 965 xor %g1, %g3, %g3 969 xor %g1, %o4, %g3 986 xor %g1, %g3, %g3 1000 ldx [%o0 + 0x00], %g1 1008 xor %g1, %g3, %g3 1012 xor %g1, %o4, %g3 1033 xor %g1, %g3, %g3 1047 ldx [%o0 - 0x10], %g1 1055 xor %g1, %g3, %g3 1059 xor %g1, %o4, %g3 1076 xor %g1, %g3, %g3 1090 ldx [%o0 - 0x10], %g1 1098 xor %g1, %g3, %g3 1102 xor %g1, %o4, %g3 1119 xor %g1, %g3, %g3 1133 ldx [%o0 - 0x10], %g1 1142 xor %g1, %g3, %g3 1146 xor %g1, %o4, %g3 1167 xor %g1, %g3, %g3 1183 ldx [%o0 + 0x00], %g1 1188 xor %g1, %g3, %g3 1211 ldx [%o0 + 0x00], %g1 1216 xor %g1, %g3, %g3 1239 ldx [%o0 + 0x00], %g1 1244 xor %g1, %g3, %g3 1265 ldx [%o0 - 0x10], %g1 1272 xor %g1, %g3, %g3 1279 xor %g1, %g3, %o0 1297 ldx [%o0 - 0x10], %g1 1304 xor %g1, %g3, %g3 1311 xor %g1, %g3, %o0 1329 ldx [%o0 - 0x10], %g1 1336 xor %g1, %g3, %g3 1343 xor %g1, %g3, %o0 1364 ldx [%o0 + 0x00], %g1 1367 1: xor %g1, %g3, %o5 1374 xor %g1, %g3, %o5 1400 10: xor %g1, %g3, %o5 1425 ldx [%o0 + 0x00], %g1 1428 1: xor %g1, %g3, %o5 1435 xor %g1, %g3, %o5 1461 10: xor %g1, %g3, %o5 1486 ldx [%o0 + 0x00], %g1 1489 1: xor %g1, %g3, %o5 1496 xor %g1, %g3, %o5 1526 xor %g1, %g3, %o5
H A D	des_asm.S	`407 1: ldx [%o1 + 0x00], %g1 418 stx %g1, [%o4 + 0x00]`
/linux-4.4.14/arch/sparc/net/
H A D	bpf_jit.h	`5 * %g1 : temporary 63 #define r_TMP %g1`
/linux-4.4.14/arch/sparc/prom/
H A D	cif.S	`34 TRAP_LOAD_THREAD_REG(%g6, %g1)`
/linux-4.4.14/arch/sparc/power/
H A D	hibernate_asm.S	`63 rd %asi, %g1 119 wr %g1, %g0, %asi`
/linux-4.4.14/crypto/
H A D	poly1305_generic.c	`219 u32 g0, g1, g2, g3, g4; crypto_poly1305_final() local 248 g1 = h1 + (g0 >> 26); g0 &= 0x3ffffff; crypto_poly1305_final() 249 g2 = h2 + (g1 >> 26); g1 &= 0x3ffffff; crypto_poly1305_final() 256 g1 &= mask; crypto_poly1305_final() 262 h1 = (h1 & mask) \| g1; crypto_poly1305_final()`
/linux-4.4.14/tools/perf/arch/sparc/util/
H A D	dwarf-regs.c	`18 "%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",`
/linux-4.4.14/arch/avr32/boards/atstk1000/
H A D	setup.c	`87 { .name = "g1:green", .gpio = GPIO_PIN_PB(10), },`
/linux-4.4.14/drivers/power/
H A D	bq27xxx_battery.c	`27 * http://www.ti.com/product/bq27530-g1 28 * http://www.ti.com/product/bq27531-g1 29 * http://www.ti.com/product/bq27541-g1 30 * http://www.ti.com/product/bq27542-g1 31 * http://www.ti.com/product/bq27546-g1 32 * http://www.ti.com/product/bq27742-g1 33 * http://www.ti.com/product/bq27545-g1 34 * http://www.ti.com/product/bq27421-g1 35 * http://www.ti.com/product/bq27425-g1 36 * http://www.ti.com/product/bq27411-g1 37 * http://www.ti.com/product/bq27621-g1`
/linux-4.4.14/arch/x86/crypto/sha-mb/
H A D	sha1_x8_avx2.S	`78 # r6 = {g7 g6 g5 g4 g3 g2 g1 g0} 83 # r1 = {h1 g1 f1 e1 d1 c1 b1 a1} 107 vshufps $0x44, \r7, \r6, \t1 # t1 = {h5 h4 g5 g4 h1 h0 g1 g0} 109 vshufps $0xDD, \t1, \r2, \r7 # r7 = {h5 g5 f5 e5 h1 g1 f1 e1}`
/linux-4.4.14/arch/cris/include/uapi/asm/
H A D	etraxgpio.h	`11 * g1-g7 and g25-g31 is both input and outputs but on different pins`
/linux-4.4.14/drivers/media/dvb-frontends/
H A D	cx24110.c	`184 static const int g1[FEC_AUTO] = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1}; cx24110_set_fec() local 217 cx24110_writereg(state, 0x1a, g1[fec]); cx24110_set_fec()`
/linux-4.4.14/drivers/usb/serial/
H A D	iuu_phoenix.c	`344 static void iuu_rgbf_fill_buffer(u8 buf, u8 r1, u8 r2, u8 g1, u8 g2, u8 b1, iuu_rgbf_fill_buffer() argument 350 buf++ = g1; iuu_rgbf_fill_buffer()`
/linux-4.4.14/include/linux/
H A D	hyperv.h	`1010 #define VMBUS_DEVICE(g0, g1, g2, g3, g4, g5, g6, g7, \ 1012 .guid = { g0, g1, g2, g3, g4, g5, g6, g7, \`
/linux-4.4.14/drivers/clk/ux500/
H A D	u8540_clk.c	`198 clk_register_clkdev(clk, NULL, "g1"); u8540_clk_init()`
/linux-4.4.14/drivers/media/platform/omap/
H A D	omap_vout.c	`110 * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3 115 * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3`
/linux-4.4.14/fs/nfsd/
H A D	nfs4state.c	`1907 static bool groups_equal(struct group_info g1, struct group_info g2) groups_equal() argument 1911 if (g1->ngroups != g2->ngroups) groups_equal() 1913 for (i=0; i<g1->ngroups; i++) groups_equal() 1914 if (!gid_eq(GROUP_AT(g1, i), GROUP_AT(g2, i))) groups_equal()`
/linux-4.4.14/drivers/media/usb/gspca/
H A D	sonixj.c	`908 {0xd1, 0x6e, 0x16, 0x85, 0x40, 0x4a, 0x40, 0x10}, /* r/g1/b/g2 gains / 943 {0xc1, 0x6e, 0x16, 0x40, 0x40, 0x40, 0x00, 0x10}, / r/g1/b gains */`

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