Searched refs:div3 (Results 1 – 7 of 7) sorted by relevance
244 clk_m_a0_div3: clk-m-a0-div3 {358 clk_m_a1_div3: clk-m-a1-div3 {480 clk_m_a2_div3: clk-m-a2-div3 {
246 clk_m_a0_div3: clk-m-a0-div3 {360 clk_m_a1_div3: clk-m-a1-div3 {482 clk_m_a2_div3: clk-m-a2-div3 {
172 atmel,master-clk-have-div3-pres;
176 atmel,master-clk-have-div3-pres;
1334 u32 div3; in aty128_set_pll() local1351 div3 = aty_ld_pll(PPLL_DIV_3); in aty128_set_pll()1352 div3 &= ~PPLL_FB3_DIV_MASK; in aty128_set_pll()1353 div3 |= pll->feedback_divider; in aty128_set_pll()1354 div3 &= ~PPLL_POST3_DIV_MASK; in aty128_set_pll()1355 div3 |= post_conv[pll->post_divider] << 16; in aty128_set_pll()1359 aty_st_pll(PPLL_DIV_3, div3); in aty128_set_pll()
221 u8 div3; member1009 pll_div3 = da7210_pll_div[cnt].div3; in da7210_set_dai_pll()
236 - atmel,master-clk-have-div3-pres : some SoC use the reserved value 7 in the